diff options
author | Michael Neuling <mikey@neuling.org> | 2021-08-04 12:50:42 +0530 |
---|---|---|
committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 11:51:25 +0530 |
commit | af5722fb0a696b74c82b52cc96f63c11bcd71df4 (patch) | |
tree | 31fc8a35e9eb7a549f0eebca649256152ca39906 /core | |
parent | b306050c1e9348972a4f7588bacbb52422d9731c (diff) | |
download | skiboot-af5722fb0a696b74c82b52cc96f63c11bcd71df4.zip skiboot-af5722fb0a696b74c82b52cc96f63c11bcd71df4.tar.gz skiboot-af5722fb0a696b74c82b52cc96f63c11bcd71df4.tar.bz2 |
p10: Workaround core recovery issue
This works around a core recovery issue in P10. The workaround involves
the CME polling for a core recovery and performing the recovery
procedure itself.
For this to happen, the host leaves core recovery off (HID[5]) and
then masks the PC system checkstop. This patch does this.
Firmware starts skiboot with recovery already off, so we just leave it
off for longer and then mask the PC system checkstop. This makes the
window longer where a core recovery can cause an xstop but this
window is still small and can still only happens on boot.
Signed-off-by: Michael Neuling <mikey@neuling.org>
[Added mambo check - Vasant]
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'core')
-rw-r--r-- | core/init.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/core/init.c b/core/init.c index 65f136d..0bf4ab2 100644 --- a/core/init.c +++ b/core/init.c @@ -47,6 +47,7 @@ #include <debug_descriptor.h> #include <occ.h> #include <opal-dump.h> +#include <xscom-p10-regs.h> enum proc_gen proc_gen; unsigned int pcie_max_link_speed; @@ -989,6 +990,38 @@ bool verify_romem(void) return true; } +static void mask_pc_system_xstop(void) +{ + struct cpu_thread *cpu; + uint32_t chip_id, core_id; + int rc; + + if (proc_gen != proc_gen_p10) + return; + + if (chip_quirk(QUIRK_MAMBO_CALLOUTS)) + return; + + /* + * On P10 Mask PC system checkstop (bit 28). This is needed + * for HW570622. We keep processor recovery disabled via + * HID[5] and mask the checkstop that it can cause. CME does + * the recovery handling for us. + */ + for_each_cpu(cpu) { + chip_id = cpu->chip_id; + core_id = pir_to_core_id(cpu->pir); + + rc = xscom_write(chip_id, + XSCOM_ADDR_P10_EC(core_id, P10_CORE_FIRMASK_OR), + PPC_BIT(28)); + if (rc) + prerror("Error setting FIR MASK rc:%d on PIR:%x\n", + rc, cpu->pir); + } +} + + /* Called from head.S, thus no prototype. */ void __noreturn __nomcount main_cpu_entry(const void *fdt); @@ -1170,6 +1203,9 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) if (proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10) cpu_set_ipi_enable(true); + /* Once all CPU are up apply this workaround */ + mask_pc_system_xstop(); + /* Add the /opal node to the device-tree */ add_opal_node(); |