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| author | Balbir Singh <bsingharora@gmail.com> | 2017-07-06 11:57:54 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-07-13 10:19:45 +1000 |
| commit | f845a648b8cb0435aa6323f58fac50792bbe1163 (patch) | |
| tree | c29f6f2e83d8289b1784285bfeadb4f9763a70fa /core/affinity.c | |
| parent | de360495f69a117cadcbffbb8ebe930014c75e2a (diff) | |
| download | skiboot-f845a648b8cb0435aa6323f58fac50792bbe1163.zip skiboot-f845a648b8cb0435aa6323f58fac50792bbe1163.tar.gz skiboot-f845a648b8cb0435aa6323f58fac50792bbe1163.tar.bz2 | |
numa/associativity: Add a new level of NUMA for GPU's
Today we have an issue where the NUMA nodes corresponding
to GPU's have the same affinity/distance as normal memory
nodes. Our reference-points today supports two levels
[0x4, 0x4] for normal systems and [0x4, 0x3] for Power8E
systems. This patch adds a new level [0x4, X, 0x2] and
uses node-id as at all levels for the GPU.
Cc: Reza Arbab <arbab@linux.vnet.ibm.com>
Cc: Alistair Popple <alistair@popple.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Balbir Singh <bsingharora@gmail.com>
Reviewed-by: Alistair Popple <alistair@popple.id.au>
Acked-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'core/affinity.c')
| -rw-r--r-- | core/affinity.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/core/affinity.c b/core/affinity.c index 9f489d3..10d483d 100644 --- a/core/affinity.c +++ b/core/affinity.c @@ -72,10 +72,10 @@ void add_associativity_ref_point(void) /* * Note about our use of reference points: * - * Linux currently supports two levels of NUMA. We use the first - * reference point for the node ID and the second reference point - * for a second level of affinity. We always use the chip ID (4) - * for the first reference point. + * Linux currently supports up to three levels of NUMA. We use the + * first reference point for the node ID and the second reference + * point for a second level of affinity. We always use the chip ID + * (4) for the first reference point. * * Choosing the second level of affinity is model specific * unfortunately. Current POWER8E models should use the DCM @@ -83,12 +83,16 @@ void add_associativity_ref_point(void) * * If there is a way to obtain this information from the FSP * that would be ideal, but for now hardwire our POWER8E setting. + * + * For GPU nodes we add a third level of NUMA, such that the + * distance of the GPU node from all other nodes is uniformly + * the highest. */ if (PVR_TYPE(mfspr(SPR_PVR)) == PVR_TYPE_P8E) ref2 = 0x3; dt_add_property_cells(opal_node, "ibm,associativity-reference-points", - 0x4, ref2); + 0x4, ref2, 0x2); } void add_chip_dev_associativity(struct dt_node *dev) |