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| author | Nicholas Piggin <npiggin@gmail.com> | 2021-08-04 12:50:40 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 11:51:25 +0530 |
| commit | 891ed8df672ddc3a38b4629aa4087f9930e1669d (patch) | |
| tree | 02f93eebfb1ff97059d5e85cd6d29342e657b7c3 /asm | |
| parent | 65714f47fb7e4d0dbf4b7d2befb5c5e86014befd (diff) | |
| download | skiboot-891ed8df672ddc3a38b4629aa4087f9930e1669d.zip skiboot-891ed8df672ddc3a38b4629aa4087f9930e1669d.tar.gz skiboot-891ed8df672ddc3a38b4629aa4087f9930e1669d.tar.bz2 | |
Initial POWER10 enablement
Co-authored-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Co-authored-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Co-authored-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Co-authored-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Co-authored-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Co-authored-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'asm')
| -rw-r--r-- | asm/head.S | 55 | ||||
| -rw-r--r-- | asm/misc.S | 4 |
2 files changed, 56 insertions, 3 deletions
@@ -324,7 +324,7 @@ boot_offset: * r28 : PVR * r27 : DTB pointer (or NULL) * r26 : PIR thread mask - * r25 : P9 fused core flag + * r25 : P9/10 fused core flag */ .global boot_entry boot_entry: @@ -342,6 +342,8 @@ boot_entry: beq 3f cmpwi cr0,%r3,PVR_TYPE_P9P beq 3f + cmpwi cr0,%r3,PVR_TYPE_P10 + beq 4f attn /* Unsupported CPU type... what do we do ? */ b . /* loop here, just in case attn is disabled */ @@ -352,8 +354,17 @@ boot_entry: mfspr %r3, SPR_SPRD andi. %r25, %r3, 1 beq 1f + b 2f - /* P8 or P9 fused -> 8 threads */ +4: /* + * P10 fused core check (SPRC/SPRD method does not work). + * PVR bit 12 set = normal code + */ + andi. %r3, %r28, 0x1000 + bne 1f + li %r25, 1 + + /* P8 or P9 fused or P10 fused -> 8 threads */ 2: li %r26,7 @@ -730,6 +741,8 @@ init_shared_sprs: beq 4f cmpwi cr0,%r3,PVR_TYPE_P9P beq 4f + cmpwi cr0,%r3,PVR_TYPE_P10 + beq 5f /* Unsupported CPU type... what do we do ? */ b 9f @@ -806,6 +819,32 @@ init_shared_sprs: LOAD_IMM64(%r3,0x00000103070F1F3F) mtspr SPR_RPR,%r3 + b 9f + +5: /* P10 */ + /* TSCR: UM recommended value */ + LOAD_IMM32(%r3,0x80287880) + mtspr SPR_TSCR, %r3 + + /* HID0: + * Boot with PPC_BIT(5) set (dis_recovery). + * Clear bit 5 to enable recovery. + */ + LOAD_IMM64(%r3, 0) + sync + mtspr SPR_HID0,%r3 + isync + + LOAD_IMM64(%r4,SPR_HMEER_P10_HMI_ENABLE_MASK) + mfspr %r3,SPR_HMEER + or %r3,%r3,%r4 + sync + mtspr SPR_HMEER,%r3 + isync + + LOAD_IMM64(%r3,0x00000103070F1F3F) + mtspr SPR_RPR,%r3 + 9: blr .global init_replicated_sprs @@ -822,6 +861,8 @@ init_replicated_sprs: beq 4f cmpwi cr0,%r3,PVR_TYPE_P9P beq 4f + cmpwi cr0,%r3,PVR_TYPE_P10 + beq 5f /* Unsupported CPU type... what do we do ? */ b 9f @@ -845,6 +886,16 @@ init_replicated_sprs: LOAD_IMM64(%r3,0x0000000000000010) mtspr SPR_DSCR,%r3 +5: /* P10 */ + /* LPCR: sane value */ + LOAD_IMM64(%r3,0x0040000000000000) + mtspr SPR_LPCR, %r3 + sync + isync + /* DSCR: Stride-N Stream Enable */ + LOAD_IMM64(%r3,0x0000000000000010) + mtspr SPR_DSCR,%r3 + 9: blr .global enter_nap @@ -99,13 +99,15 @@ cleanup_local_tlb: .global cleanup_global_tlb cleanup_global_tlb: - /* Only supported on P9 for now */ + /* Only supported on P9, P10 for now */ mfspr %r3,SPR_PVR srdi %r3,%r3,16 cmpwi cr0,%r3,PVR_TYPE_P9 beq cr0,1f cmpwi cr0,%r3,PVR_TYPE_P9P beq cr0,1f + cmpwi cr0,%r3,PVR_TYPE_P10 + beq cr0,1f blr /* Sync out previous updates */ |