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| author | Ryan Grimm <grimm@linux.vnet.ibm.com> | 2020-08-04 23:02:13 +0530 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2020-08-07 16:00:20 +1000 |
| commit | 2d065e249f78e11ddeca0c84920b28a7ca4f8ee1 (patch) | |
| tree | 0dcbaee1a6b13760e63b911cb58e61061d47e440 /asm | |
| parent | 043725d49d3b2c0b6ea3c37395aa5d6e38d5e73a (diff) | |
| download | skiboot-2d065e249f78e11ddeca0c84920b28a7ca4f8ee1.zip skiboot-2d065e249f78e11ddeca0c84920b28a7ca4f8ee1.tar.gz skiboot-2d065e249f78e11ddeca0c84920b28a7ca4f8ee1.tar.bz2 | |
Add basic P9 fused core support
P9 cores can be configured into fused core mode where two core chiplets
function as an 8-threaded, single core. So, bump four to eight in boot_entry
when in fused core mode and cpu_thread_count in init_boot_cpu.
The HID, AMOR, TSCR, RPR require the first active thread on that core chiplet
to load the copy for that core chiplet. So, send thread 1 of a fused core to
init_shared_sprs in boot_entry.
The code checks for fused core mode in the core thead state register and puts a
field in struct cpu_thread. This flag is checked when updating the HID and in
XIVE code when setting the special bar.
For XSCOM, the core ID is the non-fused EX. So, create macros to arrange the
bits. It's fairly verbose but somewhat readable.
This was tested on a P9 ZZ with 16 fused cores and ran HTX for over 24 hours.
Signed-off-by: Ryan Grimm <grimm@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Diffstat (limited to 'asm')
| -rw-r--r-- | asm/head.S | 25 |
1 files changed, 22 insertions, 3 deletions
@@ -324,6 +324,7 @@ boot_offset: * r28 : PVR * r27 : DTB pointer (or NULL) * r26 : PIR thread mask + * r25 : P9 fused core flag */ .global boot_entry boot_entry: @@ -338,13 +339,22 @@ boot_entry: cmpwi cr0,%r3,PVR_TYPE_P8NVL beq 2f cmpwi cr0,%r3,PVR_TYPE_P9 - beq 1f + beq 3f cmpwi cr0,%r3,PVR_TYPE_P9P - beq 1f + beq 3f attn /* Unsupported CPU type... what do we do ? */ b . /* loop here, just in case attn is disabled */ - /* P8 -> 8 threads */ + /* Check for fused core and set flag */ +3: + li %r3, 0x1e0 + mtspr SPR_SPRC, %r3 + mfspr %r3, SPR_SPRD + andi. %r25, %r3, 1 + beq 1f + + /* P8 or P9 fused -> 8 threads */ + 2: li %r26,7 /* Get our reloc offset into r30 */ @@ -370,6 +380,15 @@ boot_entry: #endif mtmsrd %r3,0 + /* If fused, t1 is primary chiplet and must init shared sprs */ + andi. %r3,%r25,1 + beq not_fused + + mfspr %r31,SPR_PIR + andi. %r3,%r31,1 + bnel init_shared_sprs + +not_fused: /* Check our PIR, avoid threads */ mfspr %r31,SPR_PIR and. %r0,%r31,%r26 |