interrupts: Use a #interrupt-cells of 2 for XICS interrupts

This is more compliant with PAPR, it will also allow us to
use the second cell for other attributes on P9.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

8 files changed, 42 insertions, 31 deletions

diff --git a/core/interrupts.c b/core/interrupts.c
index db39267..7109fae 100644
--- a/core/interrupts.c
+++ b/core/interrupts.c
@@ -143,7 +143,7 @@ struct dt_node *add_ics_node(void)
 	dt_add_property_strings(ics, "compatible", "IBM,ppc-xics",
 				"IBM,opal-xics");
 	dt_add_property_cells(ics, "#address-cells", 0);
-	dt_add_property_cells(ics, "#interrupt-cells", 1);
+	dt_add_property_cells(ics, "#interrupt-cells", 2);
 	dt_add_property_string(ics, "device_type",
 			       "PowerPC-Interrupt-Source-Controller");
 	dt_add_property(ics, "interrupt-controller", NULL, 0);
diff --git a/core/pci.c b/core/pci.c
index 7ba5169..cbaea35 100644
--- a/core/pci.c
+++ b/core/pci.c
@@ -1124,11 +1124,17 @@ void pci_std_swizzle_irq_map(struct dt_node *np,
 			     uint8_t swizzle)
 {
 	uint32_t *map, *p;
-	int dev, irq;
-	size_t map_size;
+	int dev, irq, esize, edevcount;
+	size_t map_size, isize;
+
+	/* Some emulated setups don't use standard interrupts
+	 * representation
+	 */
+	if (lstate->int_size == 0)
+		return;
 
 	/* Size in bytes of a target interrupt */
-	size_t isize = lstate->int_size * sizeof(uint32_t);
+	isize = lstate->int_size * sizeof(uint32_t);
 
 	/* Calculate the size of a map entry:
 	 *
@@ -1139,7 +1145,7 @@ void pci_std_swizzle_irq_map(struct dt_node *np,
 	 *
 	 * Assumption: PIC address is 0-size
 	 */
-	int esize = 3 + 1 + 1 + lstate->int_size;
+	esize = 3 + 1 + 1 + lstate->int_size;
 
 	/* Number of map "device" entries
 	 *
@@ -1150,8 +1156,6 @@ void pci_std_swizzle_irq_map(struct dt_node *np,
 	 * If we have been passed a host bridge (pd == NULL) we also
 	 * do a simple per-pin map
 	 */
-	int edevcount;
-
 	if (!pd || (pd->dev_type == PCIE_TYPE_ROOT_PORT ||
 		    pd->dev_type == PCIE_TYPE_SWITCH_DNPORT)) {
 		edevcount = 1;
diff --git a/hw/npu.c b/hw/npu.c
index f535f8a..43ec46c 100644
--- a/hw/npu.c
+++ b/hw/npu.c
@@ -1739,10 +1739,17 @@ static void npu_add_phb_properties(struct npu *p)
 	uint32_t icsp = get_ics_phandle();
 	uint64_t tkill, mm_base, mm_size;
 	uint32_t base_lsi = p->base_lsi;
-	uint32_t map[] = { 0x0, 0x0, 0x0, 0x1, icsp, base_lsi,
-			   0x0, 0x0, 0x0, 0x2, icsp, base_lsi + 1,
-			   0x800, 0x0, 0x0, 0x1, icsp, base_lsi + 2,
-			   0x800, 0x0, 0x0, 0x2, icsp, base_lsi + 3 };
+	uint32_t map[] = {
+		/* Dev 0 INT#A (used by fn0) */
+		0x0000, 0x0, 0x0, 0x1, icsp, base_lsi + NPU_LSI_INT_DL0, 1,
+		/* Dev 0 INT#B (used by fn1) */
+		0x0000, 0x0, 0x0, 0x2, icsp, base_lsi + NPU_LSI_INT_DL1, 1,
+		/* Dev 1 INT#A (used by fn0) */
+		0x0800, 0x0, 0x0, 0x1, icsp, base_lsi + NPU_LSI_INT_DL2, 1,
+		/* Dev 1 INT#B (used by fn1) */
+		0x0800, 0x0, 0x0, 0x2, icsp, base_lsi + NPU_LSI_INT_DL3, 1,
+	};
+	/* Mask is bus, device and INT# */
 	uint32_t mask[] = {0xf800, 0x0, 0x0, 0x7};
 	char slotbuf[32];
 
@@ -1759,21 +1766,8 @@ static void npu_add_phb_properties(struct npu *p)
 	dt_add_property_cells(np, "clock-frequency", 0x200, 0);
         dt_add_property_cells(np, "interrupt-parent", icsp);
 
-        /* DLPL Interrupts */
-        p->phb.lstate.int_size = 1;
-        p->phb.lstate.int_val[0][0] = p->base_lsi + NPU_LSI_INT_DL0;
-        p->phb.lstate.int_val[1][0] = p->base_lsi + NPU_LSI_INT_DL1;
-        p->phb.lstate.int_val[2][0] = p->base_lsi + NPU_LSI_INT_DL2;
-        p->phb.lstate.int_val[3][0] = p->base_lsi + NPU_LSI_INT_DL3;
-        p->phb.lstate.int_parent[0] = icsp;
-        p->phb.lstate.int_parent[1] = icsp;
-        p->phb.lstate.int_parent[2] = icsp;
-        p->phb.lstate.int_parent[3] = icsp;
-
-	/* Due to the way the emulated PCI devices are structured in
-	 * the device tree the core PCI layer doesn't do this for
-	 * us. Besides the swizzling wouldn't suit our needs even if it
-	 * did. */
+        /* DLPL Interrupts, we don't use the standard swizzle */
+	p->phb.lstate.int_size = 0;
 	dt_add_property(np, "interrupt-map", map, sizeof(map));
 	dt_add_property(np, "interrupt-map-mask", mask, sizeof(mask));
 
diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c
index 96554c8..6f5a6ab 100644
--- a/hw/p7ioc-phb.c
+++ b/hw/p7ioc-phb.c
@@ -2617,11 +2617,15 @@ static void p7ioc_pcie_add_node(struct p7ioc_phb *p)
 	 * PCI code based on the content of this structure:
 	 */
 	lsibase = p->buid_lsi << 4;
-	p->phb.lstate.int_size = 1;
+	p->phb.lstate.int_size = 2;
 	p->phb.lstate.int_val[0][0] = lsibase + PHB_LSI_PCIE_INTA;
+	p->phb.lstate.int_val[0][1] = 1;
 	p->phb.lstate.int_val[1][0] = lsibase + PHB_LSI_PCIE_INTB;
+	p->phb.lstate.int_val[1][1] = 1;
 	p->phb.lstate.int_val[2][0] = lsibase + PHB_LSI_PCIE_INTC;
+	p->phb.lstate.int_val[2][1] = 1;
 	p->phb.lstate.int_val[3][0] = lsibase + PHB_LSI_PCIE_INTD;
+	p->phb.lstate.int_val[3][1] = 1;
 	p->phb.lstate.int_parent[0] = icsp;
 	p->phb.lstate.int_parent[1] = icsp;
 	p->phb.lstate.int_parent[2] = icsp;
diff --git a/hw/p7ioc.c b/hw/p7ioc.c
index 85a0a51..4480b8e 100644
--- a/hw/p7ioc.c
+++ b/hw/p7ioc.c
@@ -629,7 +629,8 @@ static void p7ioc_create_hub(struct dt_node *np)
 	dt_add_property_cells(np, "ibm,opal-hubid", 0, id);
 
 	/* XXX Fixme: how many RGC interrupts ? */
-	dt_add_property_cells(np, "interrupts", ioc->rgc_buid << 4);
+	dt_add_property_cells(np, "interrupt-parent", get_ics_phandle());
+	dt_add_property_cells(np, "interrupts", ioc->rgc_buid << 4, 1);
 	dt_add_property_cells(np, "interrupt-base", ioc->rgc_buid << 4);
 
 	/* XXX What about ibm,opal-mmio-real ? */
diff --git a/hw/phb3.c b/hw/phb3.c
index 34e01a6..d3aae27 100644
--- a/hw/phb3.c
+++ b/hw/phb3.c
@@ -4248,11 +4248,15 @@ static void phb3_add_properties(struct phb3 *p)
 	 * PCI code based on the content of this structure:
 	 */
 	lsibase = p->base_lsi;
-	p->phb.lstate.int_size = 1;
+	p->phb.lstate.int_size = 2;
 	p->phb.lstate.int_val[0][0] = lsibase + PHB3_LSI_PCIE_INTA;
+	p->phb.lstate.int_val[0][1] = 1;
 	p->phb.lstate.int_val[1][0] = lsibase + PHB3_LSI_PCIE_INTB;
+	p->phb.lstate.int_val[1][1] = 1;
 	p->phb.lstate.int_val[2][0] = lsibase + PHB3_LSI_PCIE_INTC;
+	p->phb.lstate.int_val[2][1] = 1;
 	p->phb.lstate.int_val[3][0] = lsibase + PHB3_LSI_PCIE_INTD;
+	p->phb.lstate.int_val[3][1] = 1;
 	p->phb.lstate.int_parent[0] = icsp;
 	p->phb.lstate.int_parent[1] = icsp;
 	p->phb.lstate.int_parent[2] = icsp;
diff --git a/hw/phb4.c b/hw/phb4.c
index 220478e..0e92cc2 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -2923,11 +2923,15 @@ static void phb4_add_properties(struct phb4 *p)
 	 * PCI code based on the content of this structure:
 	 */
 	lsibase = p->base_lsi;
-	p->phb.lstate.int_size = 1;
+	p->phb.lstate.int_size = 2;
 	p->phb.lstate.int_val[0][0] = lsibase + PHB4_LSI_PCIE_INTA;
+	p->phb.lstate.int_val[0][1] = 1;
 	p->phb.lstate.int_val[1][0] = lsibase + PHB4_LSI_PCIE_INTB;
+	p->phb.lstate.int_val[1][1] = 1;
 	p->phb.lstate.int_val[2][0] = lsibase + PHB4_LSI_PCIE_INTC;
+	p->phb.lstate.int_val[2][1] = 1;
 	p->phb.lstate.int_val[3][0] = lsibase + PHB4_LSI_PCIE_INTD;
+	p->phb.lstate.int_val[3][1] = 1;
 	p->phb.lstate.int_parent[0] = icsp;
 	p->phb.lstate.int_parent[1] = icsp;
 	p->phb.lstate.int_parent[2] = icsp;
diff --git a/hw/psi.c b/hw/psi.c
index 0823ec8..46e059a 100644
--- a/hw/psi.c
+++ b/hw/psi.c
@@ -783,7 +783,7 @@ static void psi_create_mm_dtnode(struct psi *psi)
 		dt_add_property_strings(np, "compatible", "ibm,psi");
 	}
 	dt_add_property_cells(np, "interrupt-parent", get_ics_phandle());
-	dt_add_property_cells(np, "interrupts", psi->interrupt);
+	dt_add_property_cells(np, "interrupts", psi->interrupt, 1);
 	dt_add_property_cells(np, "ibm,chip-id", psi->chip_id);
 }