hw/npu2.c: Fix device aperture calculation

The POWER9 NPU2 implements an address compression scheme to compress 56-bit P9
physical addresses to 47-bit GPU addresses. System software needs to know both
addresses, unfortunately the calculation of the compressed address was
incorrect. Fix it here.

Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

1 files changed, 4 insertions, 2 deletions

diff --git a/hw/npu2.c b/hw/npu2.c
index 6513133..4ff4ba9 100644
--- a/hw/npu2.c
+++ b/hw/npu2.c
@@ -542,8 +542,10 @@ static void npu2_dn_fixup_gmb(struct dt_node *pd_dn, struct npu2_dev *ndev)
 	assert(mem_dn);
 	dt_add_property_cells(pd_dn, "memory-region", mem_dn->phandle);
 
-	gta  = ((gpu_base >> 42) & 0x1) << 41;
-	gta |= ((gpu_base >> 45) & 0x3) << 42;
+	/* Coral mode address compression. This is documented in Figure 3.5
+	 * "P9->GPU RA Compression (Coral) of the NPU2 workbook". */
+	gta  = ((gpu_base >> 42) & 0x1) << 42;
+	gta |= ((gpu_base >> 45) & 0x3) << 43;
 	gta |= ((gpu_base >> 49) & 0x3) << 45;
 	gta |= gpu_base & ((1UL << 43) - 1);