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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-09-13 13:37:26 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-09-12 22:55:12 -0500 |
| commit | a26f055af0d57a1d87f2893042be79f20594d4d9 (patch) | |
| tree | f57f486f393fb4c62b8e7ad47441b30bb41937f0 | |
| parent | db1ccfa6485d37a27c11969bcb2b463330026f40 (diff) | |
| download | skiboot-a26f055af0d57a1d87f2893042be79f20594d4d9.zip skiboot-a26f055af0d57a1d87f2893042be79f20594d4d9.tar.gz skiboot-a26f055af0d57a1d87f2893042be79f20594d4d9.tar.bz2 | |
xive: Fix opal_xive_dump_tm() to access W2 properly
The HW only supported limited access sizes.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/xive.c | 8 |
1 files changed, 7 insertions, 1 deletions
@@ -4733,7 +4733,13 @@ static int64_t opal_xive_dump_tm(uint32_t offset, const char *n, uint32_t pir) xive_regr(x, PC_TCTXT_INDIR0); v0 = in_be64(ind_tm_base + offset); - v1 = in_be64(ind_tm_base + offset + 8); + if (offset == TM_QW3_HV_PHYS) { + v1 = in_8(ind_tm_base + offset + 8); + v1 <<= 56; + } else { + v1 = in_be32(ind_tm_base + offset + 8); + v1 <<= 32; + } prlog(PR_INFO, "CPU[%04x]: TM state for QW %s\n", pir, n); prlog(PR_INFO, "CPU[%04x]: NSR CPPR IPB LSMFB ACK# INC AGE PIPR" " W2 W3\n", pir); |