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| author | Nicholas Piggin <npiggin@gmail.com> | 2021-12-17 12:24:39 +1000 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2021-12-17 10:34:23 +0100 |
| commit | 945dced9148fd98f6a84c113f9426af7b59b370b (patch) | |
| tree | b469aa8bdf44d0ad54400f20cfaccf1aac45af8d | |
| parent | 9d4ca64be70860e08259a1bced6c54bdf5cb7aa3 (diff) | |
| download | skiboot-staging.zip skiboot-staging.tar.gz skiboot-staging.tar.bz2 | |
chiptod: properly zero TB SPR when cleaning up for invalid TBstaging
The existing sequence writes TBU twice and leaves TBL unchanged. This
may not really matter if it's being resynced from the chiptod soon, but
it's possible it could clear a parity error.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| -rw-r--r-- | hw/chiptod.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/chiptod.c b/hw/chiptod.c index 7c0a1ff..736bd03 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -1556,8 +1556,9 @@ void tfmr_cleanup_core_errors(uint64_t tfmr) * restored after the next rendez-vous */ if (!(tfmr & SPR_TFMR_TB_VALID)) { + mtspr(SPR_TBWL, 0); mtspr(SPR_TBWU, 0); - mtspr(SPR_TBWU, 0); + mtspr(SPR_TBWL, 0); } } |