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author | Richard Henderson <rth@twiddle.net> | 2011-05-06 11:52:02 -0700 |
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committer | Richard Henderson <rth@twiddle.net> | 2011-05-06 11:52:02 -0700 |
commit | 87fb8be28570645cd42f940ebdaed4ee1d7724cf (patch) | |
tree | 198578397b6b6c8793ec6781263ab33418d92141 | |
parent | 2166044b7174136787fa660e7da798132f7d26cc (diff) | |
download | qemu-palcode-87fb8be28570645cd42f940ebdaed4ee1d7724cf.zip qemu-palcode-87fb8be28570645cd42f940ebdaed4ee1d7724cf.tar.gz qemu-palcode-87fb8be28570645cd42f940ebdaed4ee1d7724cf.tar.bz2 |
Use level-triggered ISA interrupts.
-rw-r--r-- | init.c | 11 | ||||
-rw-r--r-- | ioport.h | 2 |
2 files changed, 13 insertions, 0 deletions
@@ -234,6 +234,11 @@ init_pcb (void) static void init_i8259 (void) { + /* ??? MILO initializes the PIC as edge triggered; I do not know how SRM + initializes them. However, Linux seems to expect that these are level + triggered. That may be a kernel bug, but level triggers are more + reliable anyway so lets go with that. */ + /* Initialize the slave PIC. */ outb(0x11, PORT_PIC2_CMD); /* ICW1: edge trigger, cascade, ICW4 req */ outb(0x08, PORT_PIC2_DATA); /* ICW2: irq offset = 8 */ @@ -246,6 +251,12 @@ init_i8259 (void) outb(0x04, PORT_PIC1_DATA); /* ICW3: slave control INTC2 */ outb(0x01, PORT_PIC1_DATA); /* ICW4 */ + /* Initialize level triggers. The CY82C693UB that's on real alpha + hardware doesn't have this; this is a PIIX extension. However, + QEMU doesn't implement regular level triggers. */ + outb(0xff, PORT_PIC2_ELCR); + outb(0xff, PORT_PIC1_ELCR); + /* Disable all interrupts. */ outb(0xff, PORT_PIC2_DATA); outb(0xff, PORT_PIC1_DATA); @@ -53,6 +53,8 @@ #define PORT_HD_DATA 0x03f6 #define PORT_FD_DIR 0x03f7 #define PORT_SERIAL1 0x03f8 +#define PORT_PIC1_ELCR 0x04d0 +#define PORT_PIC2_ELCR 0x04d1 #define PORT_PCI_CMD 0x0cf8 #define PORT_PCI_REBOOT 0x0cf9 #define PORT_PCI_DATA 0x0cfc |