aboutsummaryrefslogtreecommitdiff
path: root/include/sbi/riscv_encoding.h
AgeCommit message (Expand)AuthorFilesLines
2024-08-01include: Adjust Sscofpmf mhpmevent mask for upper 6 bitsHEADmasterEric Lin1-1/+1
2024-06-18lib: sbi: Add support for Svade and Svadu extensionsYong-Xuan Wang1-0/+1
2024-03-19lib: sbi: Remove regs parameter from trap irq handling functionsAnup Patel1-0/+2
2024-03-05lib: sbi_misaligned_ldst: Add handling of C.LHU/C.LH and C.SHNylon Chen1-0/+7
2024-03-04lib: sbi: Add support for smcsrind and smcdelegAtish Patra1-3/+22
2024-01-10include: sbi: Add TINFO debug trigger CSRHimanshu Chauhan1-0/+1
2023-12-19lib: sbi: Refactor the code for enable extensions in menvfg CSRYong-Xuan Wang1-5/+0
2023-11-17include: sbi: macros for mseccfg.sseed and .useedHeinrich Schuchardt1-0/+4
2023-10-06lib: sbi: Add support for mconfigptrYangjie Zhang1-0/+1
2023-08-18lib: sbi: Add support for smcntrpmfKaiwen Xue1-0/+4
2023-07-31include: sbi: fix CSR define of mseccfgXiang W1-3/+2
2023-07-13include: sbi: Add macro definitions for mseccfg CSRHimanshu Chauhan1-0/+12
2023-02-27lib: sbi_hart: Enable hcontext and scontextNylon Chen1-0/+2
2022-09-01include: Remove sideleg and sedelegRahul Pathak1-2/+0
2022-08-22include: Add mstatus[h].GVA encodingsVivian Wang1-0/+4
2022-06-21lib: utils: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel1-21/+3
2022-06-21include: sbi: Add mtinst/htinst psuedoinstructionsdramforever1-0/+20
2022-06-01lib: sbi_illegal_insn: Add emulation for fence.tsoSamuel Holland1-0/+3
2022-04-28lib: sbi: Implement Sstc extensionAtish Patra1-0/+4
2022-04-17include: correct the definition of MSTATUS_VSVincent Chen1-1/+1
2022-04-11lib: sbi: Add Smstateen extension definesMayuresh Chitale1-0/+44
2022-04-05include: Add defines for [m|h|s]envcfg CSRsAnup Patel1-0/+27
2022-02-15include: sbi: Add AIA related CSR definesAnup Patel1-0/+76
2022-02-04lib: sbi: Disable interrupt during config matchingAtish Patra1-1/+2
2021-11-11lib: sbi: Support sscofpmf extension in OpenSBIAtish Patra1-0/+25
2021-11-11lib: sbi: Delegate PMU counter overflow interrupt to S modeAtish Patra1-0/+2
2021-11-11riscv: Add new CSRs introduced by Sscofpmf[1] extensionAtish Patra1-0/+34
2020-09-09include: Rename ECALL defines to match latest RISC-V specAnup Patel1-2/+2
2020-09-01include: sbi: Few cosmetic changes in riscv_encoding.hAnup Patel1-87/+139
2020-09-01lib: sbi: Improve PMP CSR detection and progammingAnup Patel1-1/+66
2020-06-08lib: Add RISC-V hypervisor v0.6.1 supportAnup Patel1-3/+12
2020-05-07lib: sbi_tlb: Fix remote TLB HFENCE VVMA implementationAnup Patel1-0/+25
2020-05-07include: sbi: Remove redundant page table related definesAnup Patel1-20/+0
2020-04-17lib: Support vector extensionAtish Patra1-0/+2
2019-12-16lib: Extend trap redirection for hypervisor v0.5 specAnup Patel1-3/+0
2019-12-16include: Add guest external interrupt related definesAnup Patel1-0/+4
2019-11-06include: Use _UL() and _ULL() for defines in riscv_encoding.hAnup Patel1-81/+79
2019-11-06include: Sync-up encoding with priv v1.12-draft and hypervisor v0.5-draftAnup Patel1-92/+45
2019-09-30lib: Emulate HTIMEDELTA CSR for platforms not having TIME CSRAnup Patel1-1/+3
2019-09-30lib: Redirect WFI trapped from VS/VU mode to HS-modeAnup Patel1-0/+3
2019-09-30lib: Extend sbi_trap_redirect() for hypervisor extensionAnup Patel1-2/+30
2019-09-30lib: Extend sbi_hart_switch_mode() to support hypervisor extensionAnup Patel1-0/+14
2019-04-24all: Annotate some tables to have clang-format leave them aloneOlof Johansson1-0/+3
2019-04-06lib: Fix the ecall macro definitionsAlistair Francis1-2/+2
2019-02-14lib: Use CSR_<FOO> instead of <foo> for csr_*()Atish Patra1-0/+8
2019-01-24all: Update copyright header in all filesAnup patel1-3/+3
2019-01-03include: Add hard FP access macros and definesAnup Patel1-0/+13
2018-12-31lib: Redirect illegal instruction trap to S-mode when not handledAnup Patel1-3/+6
2018-12-26lib: Move instruction encoding macros to riscv_encoding.hAnup Patel1-0/+117
2018-12-11Initial commit.Anup Patel1-0/+423
generated by cgit v1.1 at 2025-08-09 08:39:16 +0000