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| author | Samuel Holland <samuel@sholland.org> | 2022-06-12 20:03:55 -0500 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-06-13 11:59:09 +0530 |
| commit | 9dc5ec5c519b2ec1702e13a97b9e595ee5d94bf6 (patch) | |
| tree | f54ea6a1b99762f453616e00f35d127c9a21c58d /scripts/Kconfiglib/kconfiglib.py | |
| parent | 5e5675874ca042fe977ffb27afcfa06cadc84b8b (diff) | |
| download | opensbi-9dc5ec5c519b2ec1702e13a97b9e595ee5d94bf6.zip opensbi-9dc5ec5c519b2ec1702e13a97b9e595ee5d94bf6.tar.gz opensbi-9dc5ec5c519b2ec1702e13a97b9e595ee5d94bf6.tar.bz2 | |
platform: Add HSM implementation for Allwinner D1
Allwinner D1 contains a "PPU" power domain controller which can
automatically power down/up the CPU power domain. This power domain
includes the C906 core along with its CLINT and PLIC.
This HSM implementation supports non-retentive hart suspend by:
1) Saving/restoring state that is lost during hart suspend,
2) Performing cache maintenance before/after hart suspend,
3) Configuring wakeup sources before hart suspend, and
4) Asking the PPU to power down the hart when it enters WFI.
Since this HSM implementation is for a single-core SoC, it does not need
to worry about concurrency or saving multiple instances of state.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Diffstat (limited to 'scripts/Kconfiglib/kconfiglib.py')
0 files changed, 0 insertions, 0 deletions