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| author | Anup Patel <apatel@ventanamicro.com> | 2023-12-11 14:07:56 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-12-19 15:56:37 +0530 |
| commit | cdebae2cc9539e2e0553b9c68eab22997c734cbb (patch) | |
| tree | 3a0c68c8935b8381ba36da2eb60eaf7e350d2da1 /platform/fpga | |
| parent | 80169b25f8a9a7cb8becceff9a414900919527c6 (diff) | |
| download | opensbi-cdebae2cc9539e2e0553b9c68eab22997c734cbb.zip opensbi-cdebae2cc9539e2e0553b9c68eab22997c734cbb.tar.gz opensbi-cdebae2cc9539e2e0553b9c68eab22997c734cbb.tar.bz2 | |
lib: utils/irqchip: Add shared MMIO region for PLIC in root domain
On platforms with Smepmp, the MMIO regions accessed by M-mode need
to be explicitly marked with M-mode only read/write or shared (both
(M-mode and S-mode) read/write permission.
If the above is not done then runtime PLIC access from M-mode on
platforms with Smepmp will result in access fault when further
results in CPU hotplug not working.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Diffstat (limited to 'platform/fpga')
| -rw-r--r-- | platform/fpga/ariane/platform.c | 3 | ||||
| -rw-r--r-- | platform/fpga/openpiton/platform.c | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c index 975528f..8be5e6c 100644 --- a/platform/fpga/ariane/platform.c +++ b/platform/fpga/ariane/platform.c @@ -25,6 +25,8 @@ #define ARIANE_UART_REG_WIDTH 4 #define ARIANE_UART_REG_OFFSET 0 #define ARIANE_PLIC_ADDR 0xc000000 +#define ARIANE_PLIC_SIZE (0x200000 + \ + (ARIANE_HART_COUNT * 0x1000)) #define ARIANE_PLIC_NUM_SOURCES 3 #define ARIANE_HART_COUNT 1 #define ARIANE_CLINT_ADDR 0x2000000 @@ -36,6 +38,7 @@ static struct plic_data plic = { .addr = ARIANE_PLIC_ADDR, + .size = ARIANE_PLIC_SIZE, .num_src = ARIANE_PLIC_NUM_SOURCES, }; diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c index e59dc99..2317a89 100644 --- a/platform/fpga/openpiton/platform.c +++ b/platform/fpga/openpiton/platform.c @@ -24,6 +24,8 @@ #define OPENPITON_DEFAULT_UART_REG_WIDTH 1 #define OPENPITON_DEFAULT_UART_REG_OFFSET 0 #define OPENPITON_DEFAULT_PLIC_ADDR 0xfff1100000 +#define OPENPITON_DEFAULT_PLIC_SIZE (0x200000 + \ + (OPENPITON_DEFAULT_HART_COUNT * 0x1000)) #define OPENPITON_DEFAULT_PLIC_NUM_SOURCES 2 #define OPENPITON_DEFAULT_HART_COUNT 3 #define OPENPITON_DEFAULT_CLINT_ADDR 0xfff1020000 @@ -40,6 +42,7 @@ static struct platform_uart_data uart = { }; static struct plic_data plic = { .addr = OPENPITON_DEFAULT_PLIC_ADDR, + .size = OPENPITON_DEFAULT_PLIC_SIZE, .num_src = OPENPITON_DEFAULT_PLIC_NUM_SOURCES, }; |