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| author | Anup Patel <anup.patel@wdc.com> | 2020-05-12 10:14:43 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-05-23 10:36:26 +0530 |
| commit | 73d6ef3b2933ccf0b3a8a0ba110bf53ad9720b51 (patch) | |
| tree | baa3468336030b1680162ed4e31d3a3fa6d89179 /platform/fpga | |
| parent | 89ba63493c4ce98861144180e408d6db391fd1c3 (diff) | |
| download | opensbi-73d6ef3b2933ccf0b3a8a0ba110bf53ad9720b51.zip opensbi-73d6ef3b2933ccf0b3a8a0ba110bf53ad9720b51.tar.gz opensbi-73d6ef3b2933ccf0b3a8a0ba110bf53ad9720b51.tar.bz2 | |
lib: utils: Remove redundant parameters from PLIC init functions
The "target_hart" and "hart_count" parameters of PLIC cold and
warm init functions are only used for sanity checks and not
required in PLIC initialization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'platform/fpga')
| -rw-r--r-- | platform/fpga/ariane/platform.c | 11 | ||||
| -rw-r--r-- | platform/fpga/openpiton/platform.c | 11 |
2 files changed, 6 insertions, 16 deletions
diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c index ba9ef9d..c3f3f65 100644 --- a/platform/fpga/ariane/platform.c +++ b/platform/fpga/ariane/platform.c @@ -63,13 +63,10 @@ static int ariane_console_init(void) ARIANE_UART_REG_WIDTH); } -static int plic_ariane_warm_irqchip_init(u32 target_hart, - int m_cntx_id, int s_cntx_id) +static int plic_ariane_warm_irqchip_init(int m_cntx_id, int s_cntx_id) { size_t i, ie_words = ARIANE_PLIC_NUM_SOURCES / 32 + 1; - if (ARIANE_HART_COUNT <= target_hart) - return -1; /* By default, enable all IRQs for M-mode of target HART */ if (m_cntx_id > -1) { for (i = 0; i < ie_words; i++) @@ -99,14 +96,12 @@ static int ariane_irqchip_init(bool cold_boot) int ret; if (cold_boot) { - ret = plic_cold_irqchip_init(ARIANE_PLIC_ADDR, - ARIANE_PLIC_NUM_SOURCES, + ret = plic_cold_irqchip_init(ARIANE_PLIC_NUM_SOURCES, ARIANE_HART_COUNT); if (ret) return ret; } - return plic_ariane_warm_irqchip_init(hartid, - 2 * hartid, 2 * hartid + 1); + return plic_ariane_warm_irqchip_init(2 * hartid, 2 * hartid + 1); } /* diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c index 776ca35..781da17 100644 --- a/platform/fpga/openpiton/platform.c +++ b/platform/fpga/openpiton/platform.c @@ -95,13 +95,10 @@ static int openpiton_console_init(void) OPENPITON_DEFAULT_UART_REG_WIDTH); } -static int plic_openpiton_warm_irqchip_init(u32 target_hart, - int m_cntx_id, int s_cntx_id) +static int plic_openpiton_warm_irqchip_init(int m_cntx_id, int s_cntx_id) { size_t i, ie_words = plic.num_src / 32 + 1; - if (target_hart >= OPENPITON_DEFAULT_HART_COUNT) - return -1; /* By default, enable all IRQs for M-mode of target HART */ if (m_cntx_id > -1) { for (i = 0; i < ie_words; i++) @@ -132,13 +129,11 @@ static int openpiton_irqchip_init(bool cold_boot) if (cold_boot) { ret = plic_cold_irqchip_init(plic.addr, - plic.num_src, - OPENPITON_DEFAULT_HART_COUNT); + plic.num_src); if (ret) return ret; } - return plic_openpiton_warm_irqchip_init(hartid, - 2 * hartid, 2 * hartid + 1); + return plic_openpiton_warm_irqchip_init(2 * hartid, 2 * hartid + 1); } /* |