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| author | Anup Patel <anup.patel@wdc.com> | 2021-09-14 21:51:48 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-09-26 19:52:10 +0530 |
| commit | 12e7af9ab7ef9adf61b9138e2c38e3aeef3c140b (patch) | |
| tree | 67d388a1d7a4435060beace5dbaba32679adef41 /platform/fpga | |
| parent | 72154f4708de79816f0178b16223afa352b20e30 (diff) | |
| download | opensbi-12e7af9ab7ef9adf61b9138e2c38e3aeef3c140b.zip opensbi-12e7af9ab7ef9adf61b9138e2c38e3aeef3c140b.tar.gz opensbi-12e7af9ab7ef9adf61b9138e2c38e3aeef3c140b.tar.bz2 | |
lib: sbi: Add timer frequency to struct sbi_timer_device
Generic mdelay() and udelay() functions can be provided by the
sbi_timer framework if timer frequency is available in the timer
instance provided by the platform support or timer driver.
This patch adds timer frequency (timer_freq) member in the
struct sbi_timer_device for above purpose.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Diffstat (limited to 'platform/fpga')
| -rw-r--r-- | platform/fpga/ariane/platform.c | 2 | ||||
| -rw-r--r-- | platform/fpga/openpiton/platform.c | 7 |
2 files changed, 9 insertions, 0 deletions
diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c index 58a46c0..5acc446 100644 --- a/platform/fpga/ariane/platform.c +++ b/platform/fpga/ariane/platform.c @@ -26,6 +26,7 @@ #define ARIANE_PLIC_NUM_SOURCES 3 #define ARIANE_HART_COUNT 1 #define ARIANE_CLINT_ADDR 0x2000000 +#define ARIANE_ACLINT_MTIMER_FREQ 1000000 #define ARIANE_ACLINT_MSWI_ADDR (ARIANE_CLINT_ADDR + \ CLINT_MSWI_OFFSET) #define ARIANE_ACLINT_MTIMER_ADDR (ARIANE_CLINT_ADDR + \ @@ -44,6 +45,7 @@ static struct aclint_mswi_data mswi = { }; static struct aclint_mtimer_data mtimer = { + .mtime_freq = ARIANE_ACLINT_MTIMER_FREQ, .mtime_addr = ARIANE_ACLINT_MTIMER_ADDR + ACLINT_DEFAULT_MTIME_OFFSET, .mtime_size = ACLINT_DEFAULT_MTIME_SIZE, diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c index a9bfa99..924053e 100644 --- a/platform/fpga/openpiton/platform.c +++ b/platform/fpga/openpiton/platform.c @@ -26,6 +26,7 @@ #define OPENPITON_DEFAULT_PLIC_NUM_SOURCES 2 #define OPENPITON_DEFAULT_HART_COUNT 3 #define OPENPITON_DEFAULT_CLINT_ADDR 0xfff1020000 +#define OPENPITON_DEFAULT_ACLINT_MTIMER_FREQ 1000000 #define OPENPITON_DEFAULT_ACLINT_MSWI_ADDR \ (OPENPITON_DEFAULT_CLINT_ADDR + CLINT_MSWI_OFFSET) #define OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR \ @@ -49,6 +50,7 @@ static struct aclint_mswi_data mswi = { }; static struct aclint_mtimer_data mtimer = { + .mtime_freq = OPENPITON_DEFAULT_ACLINT_MTIMER_FREQ, .mtime_addr = OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR + ACLINT_DEFAULT_MTIME_OFFSET, .mtime_size = ACLINT_DEFAULT_MTIME_SIZE, @@ -68,6 +70,7 @@ static int openpiton_early_init(bool cold_boot) void *fdt; struct platform_uart_data uart_data; struct plic_data plic_data; + unsigned long aclint_freq; uint64_t clint_addr; int rc; @@ -83,6 +86,10 @@ static int openpiton_early_init(bool cold_boot) if (!rc) plic = plic_data; + rc = fdt_parse_timebase_frequency(fdt, &aclint_freq); + if (!rc) + mtimer.mtime_freq = aclint_freq; + rc = fdt_parse_compat_addr(fdt, &clint_addr, "riscv,clint0"); if (!rc) { mswi.addr = clint_addr; |