diff options
| author | Michael Brown <mcb30@ipxe.org> | 2012-08-23 12:38:37 +0100 |
|---|---|---|
| committer | Michael Brown <mcb30@ipxe.org> | 2012-08-23 15:15:42 +0100 |
| commit | 0e61beb26f789da01a566ff4bfdf571faacb9ce3 (patch) | |
| tree | 5f638bb47ab0e49195f27de30ce3c43a30f27b10 /src/drivers | |
| parent | 77afdc56439c904b0a8ae167a0a899c1488b328a (diff) | |
| download | ipxe-0e61beb26f789da01a566ff4bfdf571faacb9ce3.zip ipxe-0e61beb26f789da01a566ff4bfdf571faacb9ce3.tar.gz ipxe-0e61beb26f789da01a566ff4bfdf571faacb9ce3.tar.bz2 | |
[realtek] Use read-modify-write to check for C+ Command register
Some bits in the C+ Command register are always one. Testing for the
presence of the register must allow for this.
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/net/realtek.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/drivers/net/realtek.c b/src/drivers/net/realtek.c index 77df64e..f63f25f 100644 --- a/src/drivers/net/realtek.c +++ b/src/drivers/net/realtek.c @@ -879,8 +879,9 @@ static void realtek_detect ( struct realtek_nic *rtl ) { * Try to enable C+ mode and PCI Dual Address Cycle (for * 64-bit systems), if supported. */ - cpcr = ( RTL_CPCR_DAC | RTL_CPCR_MULRW | RTL_CPCR_CPRX | - RTL_CPCR_CPTX ); + cpcr = readw ( rtl->regs + RTL_CPCR ); + cpcr |= ( RTL_CPCR_DAC | RTL_CPCR_MULRW | RTL_CPCR_CPRX | + RTL_CPCR_CPTX ); writew ( cpcr, rtl->regs + RTL_CPCR ); check_cpcr = readw ( rtl->regs + RTL_CPCR ); @@ -890,7 +891,7 @@ static void realtek_detect ( struct realtek_nic *rtl ) { rtl->have_phy_regs = 1; rtl->tppoll = RTL_TPPOLL_8169; } else { - if ( check_cpcr == cpcr ) { + if ( ( check_cpcr == cpcr ) && ( cpcr != 0xffff ) ) { DBGC ( rtl, "REALTEK %p appears to be an RTL8139C+\n", rtl ); rtl->tppoll = RTL_TPPOLL_8139CP; |