summaryrefslogtreecommitdiff
path: root/UefiCpuPkg/UefiCpuPkg.ci.yaml
AgeCommit message (Collapse)AuthorFilesLines
5 daysUefiCpuPkg/UefiCpuPkg.ci.yaml: Add PrEval CI configJoey Vagedes1-0/+3
Adds an entry to the package's CI configuration file that enable policy 5 for stuart_pr_eval. With this Policy, all INFs used by the package are extracted from the provided DSC file and compared against the list of changed *.inf (INF) files in the PR. If there is a match, stuart_pr_eval will specify that this package is affected by the PR and needs to be tested. Signed-off-by: Joey Vagedes <joey.vagedes@gmail.com>
2023-02-16UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V fileSunil V L1-0/+1
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RISC-V register names do not follow the EDK2 formatting. So, add it to ignore list for now. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Ray Ni <ray.ni@intel.com>
2022-10-17UefiCpuPkg: Add R8/R9 etc in EccCheck ExceptionListTan, Dun1-1/+9
Add GENERAL_REGISTER.R8/R9 etc in EccCheck ExceptionList of UefiCpuPkg/UefiCpuPkg.ci.yaml to pass CI EccCheck.R8/R9 in structure GENERAL_REGISTER of CpuExceptionHandlerTest.h lead to EccCheck failure since no lower case characters in R8/R9/R10 etc. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
2022-08-31UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit testZhiguang Liu1-1/+3
Add host based unit tests for the CpuPageTableLib services. Unit test focuses on PageTableMap function, containing two kinds of test cases: manual test case and random test case. Manual test case creates some corner case to test function PageTableMap. Random test case generates multiple random memory entries (with random attribute) as the input of function PageTableMap to get the output pagetable. Output pagetable will be validated and be parsed to get output memory entries, and then the input and output memory entries will be compared to verify the functionality. The unit test is not perfect yet. There are options for random test, and some of them control the test coverage, and some option are not ready. Will enhance in the future. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2022-08-28Revert "UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit test"Liming Gao1-3/+1
This reverts commit 2812668bfc121ee792cf3302195176ef4a2ad0bc for tag202208. This feature will be merged after stable tag 202208 is created. Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
2022-08-16UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit testZhiguang Liu1-1/+3
Add host based unit tests for the CpuPageTableLib services. Unit test focuses on PageTableMap function, containing two kinds of test cases: manual test case and random test case. Manual test case creates some corner case to test function PageTableMap. Random test case generates multiple random memory entries (with random attribute) as the input of function PageTableMap to get the output pagetable. Output pagetable will be validated and be parsed to get output memory entries, and then the input and output memory entries will be compared to verify the functionality. The unit test is not perfect yet. There are options for random test, and some of them control the test coverage, and some option are not ready. Will enhance in the future. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-09-16UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GBAshraf Ali S1-1/+2
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when user wants to use more than 4G using 2M Page it will leads to use more number of Page table entries. using the 1-GByte Page table user can use more than 4G Memory by reducing the page table entries using 1-GByte Page, this patch attached can access memory range till 512GByte via Linear- Address Translation to a 1-GByte Page. Build Tool: if the nasm is not found it will throw Build errors like FileNotFoundError: [WinError 2]The system cannot find the file specified run the command wil try except block to get meaningful error message Test Result: Tested in both Simulation environment and Hardware both works fine without any issues. Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Cc: Sangeetha V <sangeetha.v@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Sahil Dureja <sahil.dureja@intel.com> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
2020-08-17UefiCpuPkg/UefiCpuPkg.ci.yaml: Add configuration for Ecc checkShenglei Zhang1-0/+12
Add configuration ExceptionList and IgnoreFiles for package config files. So users can rely on this to ignore some Ecc issues. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Acked-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2020-08-12UefiCpuPkg/MtrrLib/UnitTest: Add host based unit testRay Ni1-1/+11
Add host based unit tests for the MtrrLib services. The BaseLib services AsmCpuid(), AsmReadMsr64(), and AsmWriteMsr64() are hooked and provide simple emulation of the CPUID leafs and MSRs required by the MtrrLib to run as a host based unit test. Test cases are developed for each of the API. For the most important APIs MtrrSetMemoryAttributesInMtrrSettings() and MtrrSetMemoryAttributeInMtrrSettings(), random inputs are generated and fed to the APIs to make sure the implementation is good. The test application accepts an optional parameter which specifies how many iterations of feeding random inputs to the two APIs. The overall number of test cases increases when the iteration increases. Default iteration is 10 when no parameter is specified. Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Ming Shao <ming.shao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ming Shao <ming.shao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Jiewen Yao <jiewen.yao@intel.com>
2020-07-31UefiCpuPkg/UefiCpuPkg.ci.yaml: Add configuration for LicenseCheckShenglei Zhang1-0/+3
Add configuration IgnoreFiles for package config files. So users can rely on this to skip license conflict for some generated files. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-11-11UefiCpuPkg: Add YAML file for CI buildsMichael D Kinney1-0/+51
https://bugzilla.tianocore.org/show_bug.cgi?id=2315 Add YAML file to the package directory with the configuration of the checks to perform during a CI build. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>