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2021-10-13MdePkg/BaseLib: Add QuickSort function on BaseLibIanX Kuo4-1/+168
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3675 Add QuickSort function into BaseLib Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: IanX Kuo <ianx.kuo@intel.com>
2021-10-12MdePkg: Add ProcessorUpgradeSocketLGA4677 from SMBIOS 3.5.0Zeng, Star1-2/+5
This patch adds ProcessorUpgradeSocketLGA4677 definition into Smbios.h from SMBIOS 3.5.0. It also adds ProcessorUpgradeSocketLGA4189 and ProcessorUpgradeSocketLGA1200 definitions into from SMBIOS 3.4.0. Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-09-30MdePkg: CI YAML: Added new GUID to ignore duplicate listKun Qin1-1/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3629 SMM Communication PPI GUID from MdeModulePkg is defined the same as MM Communication PPI GUID from MdePkg, according to PI Spec v1.5 and onward. After introduction of MM Communication PPI definitions, an update in the ignore duplicate list is needed to avoid breaking CI build. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-09-30MdePkg: MmCommunication: Added definition of MM Communication PPIKun Qin2-0/+75
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3629 MM Communication PPI was defined in PI Specification since v1.5. This change added definition of such PPI and related GUIDs into MdePkg. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-09-29MdePkg: Fix DEVICE_SECURITY_EVENT_DATA_HEADER version definitionyi1 li1-1/+1
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3646 According to latest TCG PFP spec 1.05 revision 23, (https://trustedcomputinggroup.org/resource/pc-client-specific -platform-firmware-profile-specification/), 10.2.7 DEVICE_SECURITY_EVENT_DATA Structure, the version should be 1. Signed-off-by: yi1 li <yi1.li@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-08-30MdePkg:Update IndustryStandard/Nvme.h with Nvme amdin controller datazhoucheng1-1/+10
Update Nvme data structure Signed-off-by: Cheng Zhou <zhoucheng@phytium.com.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
2021-08-11MdePkg: Fix broken coding style in Acpi64.hChris Jones2-12/+17
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) Fix a coding style issue raised by EccCheck. This issue (error code 7008) has been fixed by moving a nested union out of its structure. Also add Acpi64.h to the "IgnoreFiles" list to stop the CI flagging naming errors present prior to ACPI 64. Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11MdePkg: Add Cache ID to PPTTChris Jones1-2/+4
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) Make changes to ACPI 6.4 header according to the latest specification: - ACPI 6.4 January 2021, Table 5.137, Table 5.140, Table 5.141 - Mantis ID 2138 (https://mantis.uefi.org/mantis/view.php?id=2138) Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11MdePkg: Add Secure Access Components in the SDEV tableChris Jones1-24/+56
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) Make changes to ACPI 6.4 header according to the latest specification: - ACPI 6.4 January 2021, Section 5.2.26.1.1 - Mantis ID 2111 (https://mantis.uefi.org/mantis/view.php?id=2111) Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11MdePkg: Add the Platform Health Assessment Table (PHAT)Chris Jones1-0/+79
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) Make changes to ACPI 6.4 header according to the latest specification: - ACPI 6.4 January 2021, Table 5.5, Section 5.2.30 - Mantis ID 2094 (https://mantis.uefi.org/mantis/view.php?id=2094) Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11MdePkg: Add Multiprocessor Wakeup structureChris Jones1-1/+28
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) Make changes to ACPI 6.4 header according to the latest specification: - ACPI 6.4 January 2021, Table 5.21, Section 5.2.12.19 - Mantis ID 2087 (https://mantis.uefi.org/mantis/view.php?id=2087) Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11MdePkg: Add 'Type 5' PCC structureChris Jones1-0/+29
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) Make changes to ACPI 6.4 header according to the latest specification: - ACPI 6.4 January 2021, Section 14.1.7, Section 14.4 - Mantis ID 2010 (https://mantis.uefi.org/mantis/view.php?id=2010) Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11MdePkg: Add flags and MinTransferSize to Generic InitiatorChris Jones1-3/+6
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) Make changes to ACPI 6.4 header according to the latest specification: - ACPI 6.4 January 2021, Table 5.59, Section 5.2.27.1 & Section 5.2.27.4 - Mantis ID 1991 (https://mantis.uefi.org/mantis/view.php?id=1991) Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11MdePkg: Remove DPPT tableChris Jones1-5/+0
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) Make changes to ACPI 6.4 header according to the latest specification: - ACPI 6.4 January 2021, Table 5.5 - Mantis ID 2133 (https://mantis.uefi.org/mantis/view.php?id=2133) Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11MdePkg: Add SPA Location Cookie field to SPA Range structureChris Jones1-0/+6
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) Make changes to ACPI 6.4 header according to the latest specification: - ACPI 6.4 January 2021, Section 5.2.25.2 System Physical Address (SPA) Range Structure, Table 5.109 - Mantis ID 1988 (https://mantis.uefi.org/mantis/view.php?id=1988) Also added a blank line between #defines and structure definitions to improve readability. Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11MdePkg: Update PMTT to ACPI 6.4Chris Jones1-42/+47
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) Make changes to ACPI 6.4 header according to the latest specification: - ACPI 6.4 January 2021, Section 5.2.21.12 - Mantis ID 1975 (https://mantis.uefi.org/mantis/view.php?id=1975) Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11MdePkg: Rename SBSA Generic Watchdog to Arm Generic WatchdogChris Jones1-7/+7
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) Make changes to ACPI 6.4 header according to the latest specification: - ACPI 6.4 January 2021, Section 5.2.24, Table 5.100 & Section 5.2.24.2 - Mantis ID 2126 (https://mantis.uefi.org/mantis/view.php?id=2126) Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11MdePkg: Increment FADT versionChris Jones1-1/+1
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) Make changes to ACPI 6.4 header according to the latest specification: - ACPI 6.4 January 2021, Table 5-9 - Mantis ID 2105 (https://mantis.uefi.org/mantis/view.php?id=2105) Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11MdePkg: Add ACPI 6.4 header fileChris Jones2-2/+2969
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516) This patch introduces a header file for the ACPI specification version 6.4. Currently it is based on the Acpi63.h header file however makes six changes: 1. Replace all occurences of "6_3"/"6.3" with "6_4/6.4". 2. Remove the trailing underscore from the header guard in accordance with the EDK2 coding standards, section 5.3.5. 3. Make Acpi64.h the latest ACPI definition included by Acpi.h. 4. Fix the BGRT Status field comment to match the ACPI 6.3A spec. 5. Fix several typos where definitions were named "PMMT" when it should be "PMTT". 6. Fix a typo: "PPTT Platform Communication Channel" should be "PDTT Platform Communication Channel". Signed-off-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-05MdePkg: add definition of LINUX_EFI_INITRD_MEDIA_GUIDJeff Brasen2-0/+35
Add LINUX_EFI_INITRD_MEDIA_GUID to our collection of GUID definitions, it can be used in a media device path to specify a Linux style initrd that can be loaded by the OS using the LoadFile2 protocol. Move these defines to MdePkg from OvmfPkg as these are relevant to non-OVMF targets as well. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2564 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-07-21MdePkg/BaseLib: Add MemoryFence implementation for RiscV64Abner Chang2-1/+24
Cc: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-20MdePkg/Include: Smbios Specification 3.4.0 changesgthotala1-10/+20
The following changes were addressed, 1. Smbios specs 3.4.0 table-51 bit5&6, these fields moved from specific MemoryArrayLocationCXLFlexbus10AddonCard to generic MemoryArrayLocationCXLAddonCard to address both CXL1.0 and 2.0 CXL revisions. 2. Smbios specs 3.4.0 table-79, The memory technology name changed from MemoryTechnologyIntelPersistentMemory to MemoryTechnologyIntelOptanePersistentMemory. Signed-off-by: Thotala Gopi <gopi.thotala@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-09MdePkg/Include: Add STATIC_ASSERT for L'' and L"" stringsMichael D Kinney1-1/+3
Add STATIC_ASSERT() macros to verify that the compiler is configured correctly for the use of L'' and L"" strings. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
2021-06-30MdePkg : Add IPMI Macro and Structure Defintions to resolve build errorsmanickavasakam karpagavinayagam2-0/+22
Build error reported for missing structures IPMI_SET_BOOT_OPTIONS_RESPONSE, EFI_IPMI_MSG_GET_BMC_EXEC_RSP, macro EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT EFI_FIRMWARE_BMC_IN_FULL_RUNTIME/EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE when using edk2-platforms\Features\Intel\OutOfBandManagement\IpmiFeaturePkg Rename EFI_IPMI_MSG_GET_BMC_EXEC_RSPB, EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE to IPMI_MSG_GET_BMC_EXEC_RSPB,IPMI_GET_BMC_EXECUTION_CONTEXT IPMI_BMC_IN_FORCED_UPDATE_MODE Signed-off-by: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com> Reviewed-by: Isaac Oram <isaac.w.oram@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-29MdePkg: MmConfiguration: Added definition of MM Configuration PPIKun Qin2-0/+65
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3440 MM Configuration PPI was defined in PI Specification since v1.5. This change added definition of such PPI and related GUIDs into MdePkg. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-29MdePkg: MmConfiguration: Move definition of EFI_MM_RESERVED_MMRAM_REGIONKun Qin2-16/+16
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3440 The definition of EFI_MM_RESERVED_MMRAM_REGION, according to PI Spec 1.5 is also referenced in EFI_PEI_MM_CONFIGURATION_PPI. Defining this structure as is will enforce any potential usage of MM Configuration PPI interface to include <Protocol/MmConfiguration.h>. This change moves this structure definition to PiMultiPhase.h, which is already included by Protocol/MmConfiguration.h through PiMmCis.h. It also paves way for introducing Ppi/MmConfiguration.h with proper dependency. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-04MdePkg/BaseLib: Fix AsmReadSs() with GCC toolchainSatoshi Tanda2-2/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3405 AsmReadSs() in Ia32/GccInlinePriv.c and X64/GccInlinePriv.c return the DS segment selector value instead of SS. Signed-off-by: Satoshi Tanda <tanda.sat@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-06-02MdePkg/MdeModulePkg: Move AML_NAME_SEG_SIZE definitionPierre Gondois1-1/+6
A NameSeg is made 4 chars. Cf. ACPI 6.4 s20.2.2 "Name Objects Encoding": NameSeg := <leadnamechar namechar namechar namechar> Notice that NameSegs shorter than 4 characters are filled with trailing underscores (‘_’s). AML_NAME_SEG_SIZE is currently defined in: - DynamicTablesPkg/Library/Common/AmlLib/AmlDefines.h - MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h Since the value can be inferred from the ACPI specification and to avoid multiple definitions, move it to MdePkg/Include/IndustryStandard/ Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-06-01MdePkg: Update DBG2 and SPCR header with NVIDIA 16550 SubtypeAshish Singhal2-0/+6
Add macros for NVIDIA 16550 UART specific debug port subtype in both DBG2 as well as SPCR header file. Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sunny Wang <sunny.wang@arm.com>
2021-06-01MdePkg: Add new 16550-compatible Serial Port Subtypes to DBG2Marcin Wojtas2-0/+6
The Microsoft Debug Port Table 2 (DBG2) specification revision May 31, 2017 adds support for 16550-compatible Serial Port Subtype with parameters defined in Generic Address Structure (GAS) [1] Reflect that in the EDK2 headers. [1] https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sunny Wang <sunny.wang@arm.com>
2021-06-01MdePkg: MmControl: Fix function and structure definition mismatchesKun Qin1-4/+4
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3397 Current Ppi/MmControl.h file has structure definition of "struct _PEI_MM_CONTROL_PPI". This name mismatches with its definition in PI Specification v1.7 (Errata) as "struct _EFI_PEI_MM_CONTROL_PPI". In addition, field types "PEI_MM_ACTIVATE" and "PEI_MM_DEACTIVATE" used in "struct _PEI_MM_CONTROL_PPI" mismatches with the definition of "EFI_PEI_MM_ACTIVATE" and "EFI_PEI_MM_DEACTIVATE" in the PI spec. This change fixes these mismatches by using the PI spec defined names. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Fixes: 6f33f7a262314af35e2b99c849e08928ea49aa55 Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-05-29MdePkg/BaseLib: add support for RMPADJUST instructionTom Lendacky4-0/+84
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The RMPADJUST instruction will be used by the SEV-SNP guest to modify the RMP permissions for a guest page. See AMD APM volume 3 for further details. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-9-brijesh.singh@amd.com>
2021-05-29MdePkg/BaseLib: add support for PVALIDATE instructionBrijesh Singh4-0/+101
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The PVALIDATE instruction validates or rescinds validation of a guest page RMP entry. Upon completion, a return code is stored in EAX, rFLAGS bits OF, ZF, AF, PF and SF are set based on this return code. If the instruction completed succesfully, the rFLAGS bit CF indicates if the contents of the RMP entry were changed or not. For more information about the instruction see AMD APM volume 3. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-8-brijesh.singh@amd.com>
2021-05-29MdePkg/Register/Amd: define GHCB macros for SNP AP creationTom Lendacky1-0/+84
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of GHCB introduces NAE for creating AP when SEV-SNP is enabled in the guest VM. See the GHCB specification, Table 5 "List of Supported Non-Automatic Events" and sections 4.1.9 and 4.3.2, for further details. While at it, define the VMSA state save area that is required for creating the AP. The save area format is defined in AMD APM volume 2, Table B-4 (there is a mistake in the table that defines the size of the reserved area at offset 0xc8 as a dword, when it is actually a word). The format of the save area segment registers is further defined in AMD APM volume 2, sections 10 and 15.5. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-7-brijesh.singh@amd.com> [lersek@redhat.com: fix typo in BZ reference]
2021-05-29MdePkg/Register/Amd: define GHCB macro for the Page State ChangeBrijesh Singh2-0/+48
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The Page State Change NAE exit will be used by the SEV-SNP guest to request a page state change using the GHCB protocol. See the GHCB spec section 4.1.6 and 2.3.1 for more detail on the structure definitions. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-6-brijesh.singh@amd.com>
2021-05-29MdePkg/Register/Amd: define GHCB macro for Register GPA structureBrijesh Singh1-0/+7
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 An SEV-SNP guest is required to perform the GHCB GPA registration. See the GHCB specification for further details. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-5-brijesh.singh@amd.com>
2021-05-29MdePkg/Register/Amd: define GHCB macros for hypervisor feature detectionBrijesh Singh2-0/+15
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of GHCB introduces advertisement of features that are supported by the hypervisor. See the GHCB spec section 2.2 for an additional details. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-4-brijesh.singh@amd.com>
2021-05-29MdePkg/Register/Amd: realign macros with more space for future expansionBrijesh Singh2-11/+11
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of the GHCB spec introduces several new SNP-specific NAEs. Unfortunately, the names for those NAEs break the alignment. Add some white spaces so that the SNP support patches do not break the alignment. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-3-brijesh.singh@amd.com>
2021-05-29MdePkg/Register/Amd: expand the SEV MSR to include the SNP definitionBrijesh Singh1-1/+6
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Define the SEV-SNP MSR bits. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-2-brijesh.singh@amd.com>
2021-05-11MdePkg/BaseRngLib: Add support for ARMv8.5 RNG instructionsRebecca Cran13-55/+602
Make BaseRngLib more generic by moving x86-specific functionality into 'Rand' and adding files under 'AArch64' to support the optional ARMv8.5 RNG instruction RNDR that is a part of FEAT_RNG. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-20MdePkg/Cpuid.h: Define new element in CPUID Leaf(07h) data structure.Jason1-3/+11
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3309 Define new element(Hybird) in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (07h) data structure. Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed: Ray Ni <ray.ni@intel.com>
2021-04-15MdePkg/Include: Allow CPU specific defines to be predefinedMichael D Kinney2-2/+17
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3308 The EDK II Build Specifications do not restrict the set of CPU architectures that can be supported. Remove places in the EDK II that assumes a fixed set of CPU architectures. Update EFI_REMOVABLE_MEDIA_FILE_NAME to allow it to be predefined in tools_def.txt or a DSC file [BuildOptions] section using a *_*_*_CC_FLAGS statement. Add support for the following two defines. If neither are defines, then preserve the current behavior. If either is defined, then compare these 16-bit values to Machine in the EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) and EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) macros. * EFI_IMAGE_MACHINE_TYPE_VALUE * EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Abner Chang <abner.chang@hpe.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-15RedfishPkg/RestJsonStructureDxe: Fix typo in function headerAbner Chang1-1/+1
In v2, BZ reference is added. BZ#:3030 Fix the typo [in]/[out] of parameter DestroyStructure in function header. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
2021-04-14MdePkg: Fix AsmReadMsr64() and AsmWriteMsr64() with GCC toolchainTakuto Naito1-4/+3
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3325 1. AsmReadMsr64() in X64/GccInlinePriv.c AsmReadMsr64 can return uninitialized value if FilterBeforeMsrRead returns False. This causes build error with the CLANG toolchain. 2. AsmWriteMsr64() in X64/GccInlinePriv.c In the case that FilterBeforeMsrWrite changes Value and returns True, The original Value, not the changed Value, is written to the MSR. This behavior is different from the one of AsmWriteMsr64() in X64/WriteMsr64.c for the MSFT toolchain. Signed-off-by: Takuto Naito <naitaku@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-13MdePkg: Allow PcdFSBClock to by DynamicAnthony PERARD1-4/+4
We are going to want to change the value of PcdFSBClock at run time in OvmfXen, so move it to the PcdsDynamic section. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490 Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20210412133003.146438-3-anthony.perard@citrix.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-08MdePkg/Baseib: Filter/trace MSR access for IA32/X64Dandan Bi7-43/+129
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-04-08MdePkg/IoLib: Filter/trace port IO/MMIO accessDandan Bi9-73/+329
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-04-06MdePkg/BaseLib: Add support for the XSETBV instructionJiaxin Wu4-2/+95
*v2: refine the coding format. https://bugzilla.tianocore.org/show_bug.cgi?id=3284 This patch is to support XSETBV instruction so as to support Extended Control Register(XCR) write. Extended Control Register(XCR) read has already been supported by below commit to support XGETBV instruction: 9b3ca509abd4e45439bbdfe2c2fa8780c950320a Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ni Ray <ray.ni@intel.com> Cc: Yao Jiewen <jiewen.yao@intel.com> Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com> Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-01MdePkg/Include/Protocol: EFI_RESET_NOTIFICATION_PROTOCOL duplicateMichael D Kinney1-3/+3
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3286 Remove duplicate declaration of structure type EFI_RESET_NOTIFICATION_PROTOCOL from ResetNotification.h. The forward declaration of the top of this file already declared this type. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-01MdePkg/Include/Protocol: EFI_HII POPUP_PROTOCOL duplicate declarationMichael D Kinney1-3/+3
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3285 Remove duplicate declaration of structure type EFI_HII_POPUP_PROTOCOL from HiiPopup.h. The forward declaration of the top of this file already declared this type. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
generated by cgit v1.1 at 2024-08-01 01:32:39 +0000