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2024-04-09IntelFsp2Pkg: Fsp T new ARCH UPD SupportDuggapu Chinni B1-13/+54
Changes to support spec changes 1. Remove usage of Pcd. 2. Change code to validate the Temporary Ram size input. 3. Consume the input saved in YMM Register Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chiu Chasel <chasel.chiu@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Ni Ray <ray.ni@intel.com> Signed-off-by: Duggapu Chinni B <chinni.b.duggapu@intel.com> Reviewed-by: Chiu Chasel <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2023-04-04IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.Chasel Chiu1-21/+24
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391 FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return directly without parsing rest of the microcode in FV. This patch also removed unnecessary LoadCheck code after supporting CPU microcode already loaded scenario. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2023-03-24IntelFsp2Pkg: Fix NASM X64 build warnings.Chasel Chiu2-11/+9
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4377 Fix below warnings generated by NASM X64 build: /X64/FspHelper.iii:26: warning: signed dword value exceeds bounds /X64/FspHelper.iii:35: warning: signed dword value exceeds bounds /X64/FspApiEntryT.iii:320: warning: dword data exceeds bounds Also replaced "cmp reg, 0" with "test reg, reg" per optimization suggestion. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-11-11IntelFsp2Pkg: Improvement of supporting null UPD pointer in FSP-TKuo, Ted1-1/+3
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4114 1.Use xmm5 slot 1 and xmm6 slot 3 to save ucode status and UPD pointer respectively in TempRamInitApi in IA32 FspSecCoreT. 2.Correct inappropriate description in the return value of AsmGetFspInfoHeader. 3.Replace hardcoded offset value 0x1C with FSP_HEADER_IMGBASE_OFFSET in FspHeler.nasm. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-11-04IntelFsp2Pkg: FSP should support input UPD as NULL.Chasel Chiu1-14/+26
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4114 FSP specification supports input UPD as NULL cases which FSP will use built-in UPD region instead. FSP should not return INVALID_PARAMETER in such cases. In FSP-T entry point case, the valid FSP-T UPD region pointer will be passed to platform FSP code to consume. In FSP-M and FSP-S cases, valid UPD pointer will be decided when updating corresponding pointer field in FspGlobalData. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Ted Kuo <ted.kuo@intel.com>
2022-09-15IntelFsp2Pkg: Fix FspSecCoreI build failure.Chasel Chiu1-0/+11
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4049 Link error occurred in certain compiling environment when building FspSecCoreI: unresolved external symbol _TempRamInitApi. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-09-15IntelFsp2Pkg: NvsBufferPtr is missing in Fsp24ApiEntryM.nasmKuo, Ted1-1/+2
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4063 Added NvsBufferPtr to FSPM_UPD_COMMON_FSP24 in Fsp24ApiEntryM.nasm to align with FSP 2.4 SPEC. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2022-09-07IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions.Chasel Chiu3-0/+414
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916 Adopt MultiPhase functions for both FspSecCoreS and FspSecCoreM. For backward compatibility, new INF are created for new modules. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-08-15IntelFsp2Pkg: FSPM_ARCH2_UPD mismatching bug.Chasel Chiu1-1/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4019 FSPM_ARCH2_UPD in FspApiEntryM.nasm was not up-to-date and should be fixed for both IA32 and X64 builds. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2022-07-20IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support.Hongbin1 Zhang4-8/+52
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993 Add FSP-I API entry point for SMM support. Also update 64bit API entry code to assign ApiIdx to RAX to avoid confusion. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-05-31IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling ConventionDuggapu, Chinni B1-19/+20
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926 This API accept one parameter using RCX and this is consumed in mutiple sub functions. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: cbduggap <chinni.b.duggapu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2022-04-16IntelFsp2Pkg: FspSecCore support for X64Ted Kuo9-0/+1152
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FspSecCore support for X64. 2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported. 3.Corrected few typos. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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