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| author | Kuo, Ted <ted.kuo@intel.com> | 2022-11-09 03:30:57 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-11-11 04:46:39 +0000 |
| commit | 3182843f3bc92599fa2ed4fd13ffd3f75907fe9e (patch) | |
| tree | fbefc5018646a9e888198f0b79b39e4740c7d402 /IntelFsp2Pkg/FspSecCore/X64 | |
| parent | c8fb7240469b5753773da4fa5710b870b790c363 (diff) | |
| download | edk2-3182843f3bc92599fa2ed4fd13ffd3f75907fe9e.zip edk2-3182843f3bc92599fa2ed4fd13ffd3f75907fe9e.tar.gz edk2-3182843f3bc92599fa2ed4fd13ffd3f75907fe9e.tar.bz2 | |
IntelFsp2Pkg: Improvement of supporting null UPD pointer in FSP-T
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4114
1.Use xmm5 slot 1 and xmm6 slot 3 to save ucode status and UPD pointer
respectively in TempRamInitApi in IA32 FspSecCoreT.
2.Correct inappropriate description in the return value of
AsmGetFspInfoHeader.
3.Replace hardcoded offset value 0x1C with FSP_HEADER_IMGBASE_OFFSET in
FspHeler.nasm.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com>
Signed-off-by: Ted Kuo <ted.kuo@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'IntelFsp2Pkg/FspSecCore/X64')
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm index 122fa1d..71624a3 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm @@ -7,10 +7,12 @@ DEFAULT REL
SECTION .text
+FSP_HEADER_IMGBASE_OFFSET EQU 1Ch
+
global ASM_PFX(AsmGetFspBaseAddress)
ASM_PFX(AsmGetFspBaseAddress):
call ASM_PFX(AsmGetFspInfoHeader)
- add rax, 0x1C
+ add rax, FSP_HEADER_IMGBASE_OFFSET
mov eax, [rax]
ret
|