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2017-02-21ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissionsArd Biesheuvel1-8/+0
Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, add support for this in the AARCH64 MMU code. Move the EFI_MEMORY_CACHETYPE_MASK macro to a shared location between CpuDxe and ArmMmuLib so we don't have to introduce yet another definition. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-02-21ArmPkg/CpuDxe: ARM: ignore page table updates that only change permissionsArd Biesheuvel1-0/+7
Currently, we have not implemented support on 32-bit ARM for managing permission bits in the page tables. Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, let's simply ignore those for now. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-02-21ArmPkg/CpuDxe: translate invalid memory types in EfiAttributeToArmAttributeArd Biesheuvel2-6/+1
The single user of EfiAttributeToArmAttribute () is the protocol method EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes(), which uses the return value to compare against the ARM attributes of an existing mapping, to infer whether it is actually necessary to change anything, or whether the requested update is redundant. This saves some cache and TLB maintenance on 32-bit ARM systems that use uncached translation tables. However, EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() may be invoked with only permission bits set, in which case the implied requested action is to update the permissions of the region without modifying the cacheability attributes. This is currently not possible, because EfiAttributeToArmAttribute () ASSERT()s [on AArch64] on Attributes arguments that lack a cacheability bit. So let's simply return TT_ATTR_INDX_MASK (AArch64) or TT_DESCRIPTOR_SECTION_TYPE_FAULT (ARM) in these cases (or'ed with the appropriate permission bits). This way, the return value is equally suitable for checking whether the attributes need to be modified, but in a way that accommodates the use without a cacheability bit set. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-02-21ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usageJiewen Yao3-11/+11
Current Arm CpuDxe driver uses EFI_MEMORY_WP for write protection, according to UEFI spec, we should use EFI_MEMORY_RO for write protection. The EFI_MEMORY_WP is the cache attribute instead of memory attribute. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2017-02-07ArmPkg/GenericWatchdogDxe: Declare MMIO PCDs as UINT64Alexei1-5/+5
PcdGenericWatchdogControlBase & PcdGenericWatchdogRefreshBase are declared as UINT32 values in ArmPkg.dec, but for platforms with addresses in the memory range above 4GB this causes build error F000: Too large PCD value for datum type [UINT32] of PCD gArmTokenSpaceGuid.PcdGenericWatchdogControlBase Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=361 Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2017-01-20ArmPkg/ArmLib: remove indirection layer from timer register accessorsArd Biesheuvel1-1/+0
The generic timer support libraries call the actual system register accessor function via a single pair of functions ArmArchTimerReadReg() and ArmArchTimerWriteReg(), which take an enum argument to identify the register, and return output values by pointer reference. Since these functions are never called with a non-immediate argument, we can simply replace each invocation with the underlying system register accessor instead. This is mostly functionally equivalent, with the exception of the bounds check for the enum (which is pointless given the fact that we never pass a variable), the check for the presence of the architected timer (which only makes sense for ARMv7, but is highly unlikely to vary between platforms that are similar enough to run the same firmware image), and a check for enum values that refer to the HYP view of the timer, which we never referred to anywhere in the code in the first place. So get rid of the middle man, and update the ArmGenericTimerPhyCounterLib and ArmGenericTimerVirtCounterLib implementations to call the system register accessors directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
2016-11-02ArmPkg/CpuDxe: set DmaBufferAlignment according to CWGArd Biesheuvel1-1/+12
The DmaBufferAlignment currently defaults to 4, which is dangerously small and may result in lost data on platforms that perform non-coherent DMA. So instead, take the CWG value from the cache info registers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-10-28ArmPkg/ArmCortexA9Lib RVCT: remove incompatible GCC includeArd Biesheuvel1-4/+0
Drop the include of AsmMacroIoLib.h, which contains GCC preprocessor macros that RVCT does not use or require, given it has its own AsmMacroIoLib.inc Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-26ArmPkg/CpuDxe: Fix MMU initialization problemKurt Kennett1-0/+5
During Mmu initialization in the CpuDxe, for a page table any bits set in the 'NextSectionAttributes' are garbage and were set from bits that are actually part of the pagetable address. We clear it out to zero so that the SyncCacheConfigPage will use the page attributes instead of trying to convert the (bogus) section attributes into page attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kurt Kennett <kurt.kennett@microsoft.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-09-09ArmPkg/ArmGicLib: use correct loop variableArd Biesheuvel1-1/+1
The ArmGicLib API function GicGetCpuRedistributorBase () declares GicCpuRedistributorBase to iterate over the redistributors of all CPUs, but then inadvertently advances GicRedistributorBase instead. Reported-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08ArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-upDennis Chen2-4/+4
According to the ACPI 6.0/6.1 spec, the physical base address of GICC, GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC base address PCDs to 64-bit, and fix up all users. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Dennis Chen <dennis.chen@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-08-11ArmPkg/ArmGicV3: switch to ASM_FUNC() asm macroArd Biesheuvel2-40/+16
Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-11ArmPkg/ArmCpuLib: switch to ASM_FUNC() asm macroArd Biesheuvel2-15/+3
Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-08ArmPkg/ArmGicDxe: Fix double GIC EIOR write per interruptAlexei Fedorov2-6/+4
This commit fixes a bug in the GIC v2 and v3 drivers where the GICC_EOIR (End Of Interrupt Register) is written twice for a single interrupt. GicV(2|3)IrqInterruptHandler() calls the Interrupt Handler and then GicV(2|3)EndOfInterrupt() on exit: InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt]; if (InterruptHandler != NULL) { // Call the registered interrupt handler. InterruptHandler (GicInterrupt, SystemContext); } else { DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt)); } GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt); although gInterrupt->EndOfInterrupt() can be expected to have already been called by InterruptHandler() [which is the case for the primary in-tree handler in TimerDxe] The fix moves the EndOfInterrupt() call inside the else case for unregistered/spurious interrupts. This removes a potential race condition that might have lost interrupts. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-07-13ArmPkg/ArmGicLib: manage GICv3 SPI state at the distributorArd Biesheuvel1-3/+22
Unlike SGIs and PPIs, which are private to the CPU and are managed at the redistributor level (which is also a per-CPU construct), shared interrupts (SPIs) are shared between all CPUs, and therefore managed at the distributor level (just as on GICv2). Reported-by: Narinder Dhillon <ndhillonv2@gmail.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-07-11ArmPkg: Fix typos in commentsGiri P Mudusuru1-1/+1
EFI_UNSUPPORTEDT to EFI_UNSUPPORTED Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-07-07ArmPkg ArmVirtPkg MdeModulePkg: switch to separate ArmMmuLibArd Biesheuvel1-0/+1
Switch all users of ArmLib that depend on the MMU routines to the new, separate ArmMmuLib. This needs to occur in one go, since the MMU routines are removed from ArmLib build at the same time, to prevent conflicting symbols. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-07-01ArmPkg/CpuDxe: unmask SErrors in DEBUG buildsArd Biesheuvel1-0/+9
SErrors (formerly called asynchronous aborts) are a distinct class of exceptions that are not closely tied to the currently executing instruction. Since execution may be able to proceed in such a condition, this class of exception is masked by default, and software needs to unmask it explicitly if it is prepared to handle such exceptions. On DEBUG builds, we are well equipped to report the CPU context to the user and it makes sense to report an SError as soon as it occurs rather than to wait for the OS to take it when it unmasks them, especially since the current arm64/Linux implementation simply panics in that case. So unmask them when ArmCpuDxe loads. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-06-23ArmPkg/ArmGicV3Dxe: configure all interrupts as non-secure Group-1Ard Biesheuvel1-0/+16
Reassign all interrupts to non-secure Group-1 if the GIC has its DS (Disable Security) bit set. In this case, it is safe to assume that we own the GIC, and that no other firmware has performed any configuration yet, which means it is up to us to reconfigure the interrupts so they can be taken by the non-secure firmware. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-04-29ArmPkg: implement CpuIo2 protocol driver specific for PCIArd Biesheuvel2-0/+612
The CpuIo2 protocol is required by the generic PciHostBridgeDxe driver, which relies on it to back its own I/O and MMIO operations. Since ARM has no native I/O port equivalent, such accesses can only originate from PCI drivers, and the PCI I/O space is translated to MMIO in this case. So we can implement this protocol using MMIO operations only, and take the PCI I/O translation offset into account when performing I/O port accesses. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-04-25ArmPkg/Gic: Fix boundary checking bugHeyi Guo3-9/+9
mGicNumInterrupts is the total number of interrupts, so the interrupt ID equal to mGicNumInterrupts is also invalid. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-03-25ArmPkg: apply Cortex-A57 errataLeendert van Doorn1-3/+6
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-03-17ArmPkg: update CpuDxe to use CpuExceptionHandlerLibCohen, Eugene7-1402/+98
Use the new ARM/AArch64 implementation of the base CpuExceptionHandlerLib library from CpuDxe to centralize exception handling. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-02-23ArmPkg: CpuDxe: don't track interrupt state in a global variableCohen, Eugene1-5/+1
Update the CpuDxe driver to remove an assumption that it is the only component modifying interrupt state since this can be done through BaseLib as well. Instead of using a global variable for last interrupt state we now check the current PSTATE value directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-01-30ArmPkg: Rectify file modesEvan Lloyd2-0/+0
Problems have been encountered because some of the source files have execute permission set. This can cause git to report them as changed when they are checked out onto a file system with inherited permissions. This has been seen using Cygwin, MinGW and PowerShell Git. This patch makes no change to source file content, and only aims to correct the file modes/permissions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19778 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15ArmPkg: use unified asm syntax for CLANGArd Biesheuvel1-4/+5
The CLANG assembler does not support the legacy, non-unified assembler syntax, i.e., it does not support the reordering of the condition suffixes with the increment/decrement before/after or byte/word suffixes, and it does not recognize the 'empty descending' (ED) suffix at all. So move to the unified syntax, and replace 'empty descending' with 'decrement after' or 'increment before' as appropriate. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19280 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15ArmPkg/ArmGic: fix bug in GICv3 distributor configurationArd Biesheuvel1-2/+2
In the function ArmGicEnableDistributor (), the Affinity Routing Enable (ARE) bit, which essentially defines whether the GIC runs in v2 or v3 mode, is inadvertently cleared when enabling the GIC distributor if it is running in v3 mode. So fix that. Reported-by: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19274 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15ArmPkg/CpuDxe: drop ARMv4 exception handling codeArd Biesheuvel7-357/+4
Since we do not support anything below ARMv7, let's promote the ARMv6 exception handling code in CpuDxe to the only version we provide for ARM. This means we can drop the unused ARMv4 version. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19273 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-03ArmPkg: update RVCT assembly functions to use new RVCT_ASM_EXPORT macroEugene Cohen2-20/+11
This has the effect of splitting assembly functions into their own sections so the linker can remove unused ones to save space. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@gmail.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19109 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-19ArmPkg/ArmPlatformPkg: position vectors relative to baseMark Rutland1-20/+20
We currently rely on .align directives to ensure that each exception vector entry is the appropriate offset from the vector base address. This is slightly fragile, as were an entry to become too large (greater than 32 A64 instructions), all following entries would be silently shifted until they meet the next alignment boundary. Thus we might execute the wrong code in response to an exception. To prevent this, introduce a new macro, VECTOR_ENTRY, that uses .org directives to position each entry at the precise required offset from the base of a vector. A vector entry which is too large will trigger a build failure rather than a runtime failure which is difficult to debug. For consistency, the base and end of each vector is similarly annotated, with VECTOR_BASE and VECTOR_END, which provide the necessary alignment and symbol exports. The now redundant directives and labels are removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18904 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-06ArmPkg: Purge unused/unneeded CPU-specific header filesLeif Lindholm2-2/+4
In ArmPkg/Include/Chipset, several CPU-specific header files reside. Most of these provide no actual, or very little, use. ARM1176JZ-S.h is not used at all (and unusable since SVN r18237). ArmAemV8.h simply includes AArch64.h. ArmCortexA15.h defines one processor-specific configuration bit and then includes ArmV7.h. Delete these include files, and update their sole users to function without them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18736 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-24ArmPkg/CpuDxe: Disable interrupt before restoring contextHeyi Guo1-0/+8
Interrupt must be disabled before we storing ELR and other system registers, or else ELR will be overridden by interrupt reentrance. This bug is critical as we may get occasional exception or dead loop when interrupt reentrance occurs: After increasing SP ... Before popping out registers Or After restoring ELR The 1st circumstance could also be resolved by optimizing SP operation (Pop out registers before adding SP back), but the 2nd could not be resolved by disabling interrupt. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18538 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-19ArmPkg: remove ARMv6 support codeArd Biesheuvel2-69/+0
No platforms use the ARMv6 (ARM11) support code anymore. In fact, the only reference to it in ArmPkg.dsc was commented out by Andrew in SVN r11298 (2011-02-03) so it may well be broken. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18237 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-10ArmPkg/GenericWatchdogDxe: add missing VOID* castArd Biesheuvel1-1/+1
Use an explicit VOID* cast when passing a static char array into a function taking a void pointer. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18193 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-10ArmPkg/GicV3: use GICv3 generic sysreg names only for GNU asArd Biesheuvel1-0/+10
The GNU assembler extends the generic notation for IMPLEMENTATION DEFINED system registers to support any system register, so that system registers defined by newer versions of the architecture can still be used by older versions of the toolchain. Clang before v3.6 supports the generic notation, but does not support this extension, nor does it need to in the particular case of the GICv3 support code, since it knows the GICv3 registers by their architectural names. So only redefine their real names to their generic aliases if we are not using clang. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18192 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28ArmPkg: split off ArmGicArchLib from ArmGicLibArd Biesheuvel4-106/+2
The current implementation of ArmGicGetSupportedArchRevision () that is used by all ARM platforms is entirely stateless (in order to support being executed from flash) so it needs to interrogate the hardware for the supported GIC revision upon each invocation. However, this statelessness is only needed for SEC type modules; in all other cases, we could easily determine the GIC revision once, and store the result in a global variable. In preparation of having separate early and normal versions, this patch introduces the ArmGicArchLib library class and default implementation, and moves the existing ArmGicGetSupportedArchRevision () into it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18098 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28ArmPkg: merge ArmGicV[23]Lib.h into ArmGicLib.hArd Biesheuvel8-133/+4
Before splitting off ArmGicArchLib and moving it out of ArmPkg/Drivers/ArmGic into ArmPkg/Library, make sure that the GIC specific declarations it depends on are not hidden away in local headers "GicV2/GicV2Lib.h" and "GicV3/GicV3Lib.h". So merge them with <Library/ArmGicLib.h>. This is entirely appropriate, since this is not a header that declares a public interface into ArmGicLib, but defines implementation internals. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18097 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-06ArmPkg/CpuDxe: Fixed AArch64 MMUOlivier Martin1-0/+3
When the function that determines the size of a contiguous region was returning from a sub-level table scanning it was forgetting to move to the next entry of its own level table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <Olivier.Martin@arm.com> Reviewed-by: Ronald Cron <Ronald.Cron@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17832 6f19259b-4bc3-4df7-8a09-765794883524
2015-06-09ArmPkg: reduce sysreg access count in GIC revision probeArd Biesheuvel2-4/+16
Accesses to system registers are disproportionately heavy-weight when executed under virtualization, since each one involves two world switches (from guest to host and back again). So change the sequence that enables the GIC SRE interface so that it performs only a single sysreg read to test whether the SRE interface is enabled already, and only performs a write and an additional read if that turns out not to be the case. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17596 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-28ArmPkg: allow HYP timer interrupt to be omittedArd Biesheuvel1-3/+11
The DT binding for the ARM generic timer describes the secure, non-secure, virtual and hypervisor timer interrupts, respectively. However, under virtualization, only the virtual timer is usable, and the device tree may omit the hypervisor timer interrupt. (Other timer interrupts cannot be omitted simply due to the fact that the virtual timer is listed third) Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16953 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-25ArmPkg/ArmGic: Fix GICv3 in GICv2 legacy modeOlivier Martin2-6/+30
- GIC distributor needs to be programmed to target interrupts on the boot CPU using the Interrupt Processor Targets Registers - Enabling the GIC Distributor is different following the value of GICD_CTLR.ARE_NS. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16926 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-16ArmPkg/ArmGic: enable ARE bit before driving GICv3 in native modeArd Biesheuvel5-4/+19
The GICv3 driver must use native mode to drive a GICv3 due to the fact that v2 compatibility is optional in the v3 spec. However, if v2 compatibility is implemented, it is the default and needs to be disabled first by setting the Affinity Routing Enable (ARE) bit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> [added PCD that allows forcing the GICv3 driver to drive the GIC in v2 mode] Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16875 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-16ArmPkg/ArmGic: Use the GIC Redistributor instead of GIC Distributor for GICv3Olivier Martin5-38/+84
GICv3 controller with no GICv2 legacy support must use the GIC Redistributor registers instead of the GIC Distributor registers for some operations (eg: enable/disable interrupts). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16874 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-16ArmPkg/ArmGic: Function to locate the current CPU GIC redistributorOlivier Martin3-3/+64
CPU GIC Registributors are located next to each other in the GIC Redistributor space. The CPU GIC Redistributor is identified by its CPU affinity Aff3.Aff2.Aff1.Aff0. This function returns the base address of the GIC Redistributor of the calling CPU. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16873 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-16ArmPkg/ArmGic: Added GICv3 specific definitionsOlivier Martin2-3/+6
ARM GICv3 specification introduces some new components and registers. This patch adds their definitions. The most important GICv3 component is the GIC Redistributor. It supports LPIs (Locality-specific peripheral Interrupt), 8+ CPU configuration. Some GIC distributor registers have moved to the GIC redistributor. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16872 6f19259b-4bc3-4df7-8a09-765794883524
2014-12-12ArmPkg/GenericWatchdogDxe: Set up the watchdog timeout relatively to the ↵Ronald Cron1-3/+3
system counter Use the system counter to compute the watchdog compare value as the watchdog compare value is compared to the system counter to check if the watchdog timeout expired or not. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16513 6f19259b-4bc3-4df7-8a09-765794883524
2014-12-12ArmPlatformPkg/ArmJunoPkg: Move the watchdog generic driver to ArmPkg/DriversRonald Cron3-0/+436
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16512 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-13ArmPkg/ArmGicLib: select GICv2 mode if SRE is present but unavailableArd Biesheuvel3-10/+26
Even if the CPU id registers indicate hardware support for the System Register interface to the GIC, higher exception levels may disable that interface and only allow access through MMIO. So move the enabling of the SRE bit to the GIC version detection routine: if we trigger an exception, we would have anyway at a later stage, so the net effect is the same. However, if setting the bit doesn't stick, it means we can switch to MMIO and proceed normally otherwise. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16344 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-13ArmPkg/ArmGic: Removed 'GCC' toolchain to build assembly filesOlivier Martin2-2/+2
ARMCC6 toolchain (LLVM based) understands the GNU assembly language. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16343 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/ArmGic: Added GicV3 support to ArmGicDxeOlivier Martin10-63/+350
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16234 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.1 at 2024-11-16 02:50:16 +0000