diff options
Diffstat (limited to 'UefiCpuPkg')
34 files changed, 878 insertions, 551 deletions
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c index 4f9d53e..6bbcdac 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c @@ -331,19 +331,17 @@ InitializeCpu ( IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
-
- GetFirmwareContextPointer (&FirmwareContext);
- ASSERT (FirmwareContext != NULL);
- if (FirmwareContext == NULL) {
- DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_CONTEXT\n"));
- return EFI_NOT_FOUND;
- }
+ EFI_STATUS Status;
+ VOID *Hob;
+ RISCV_SEC_HANDOFF_DATA *SecData;
+ const EFI_GUID SecHobDataGuid = RISCV_SEC_HANDOFF_HOB_GUID;
+
+ Hob = GetFirstGuidHob (&SecHobDataGuid);
+ ASSERT (Hob != NULL);
- DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __func__, FirmwareContext));
+ SecData = GET_GUID_HOB_DATA (Hob);
+ mBootHartId = SecData->BootHartId;
- mBootHartId = FirmwareContext->BootHartId;
DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n", __func__, mBootHartId));
InitializeCpuExceptionHandlers (NULL);
@@ -362,8 +360,7 @@ InitializeCpu ( //
// Initialize FPU
//
- Status = RiscVInitializeFpu ();
- ASSERT_EFI_ERROR (Status);
+ InitializeFloatingPointUnits ();
//
// Install Boot protocol
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h index 0c4ef2e..347c6ed 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h @@ -12,16 +12,18 @@ #include <PiDxe.h>
+#include <Guid/RiscVSecHobData.h>
#include <Protocol/Cpu.h>
#include <Protocol/RiscVBootProtocol.h>
-#include <Library/BaseRiscVFpuLib.h>
#include <Library/BaseRiscVSbiLib.h>
#include <Library/BaseRiscVMmuLib.h>
#include <Library/TimerLib.h>
#include <Library/BaseLib.h>
#include <Library/CacheMaintenanceLib.h>
#include <Library/CpuExceptionHandlerLib.h>
+#include <Library/CpuLib.h>
#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Register/RiscV64/RiscVEncoding.h>
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf index 7600c88..6342499 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf @@ -38,7 +38,6 @@ PeCoffGetEntryPointLib
RiscVSbiLib
RiscVMmuLib
- RiscVFpuLib
CacheMaintenanceLib
TimerLib
diff --git a/UefiCpuPkg/Include/Guid/RiscVSecHobData.h b/UefiCpuPkg/Include/Guid/RiscVSecHobData.h new file mode 100644 index 0000000..ddfba64 --- /dev/null +++ b/UefiCpuPkg/Include/Guid/RiscVSecHobData.h @@ -0,0 +1,22 @@ +/** @file
+ RISC-V SEC Data Hob to pass booting information between SEC, PEI and DXE.
+
+ Copyright (c) 2025, Ventana Micro Systems Inc.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_SEC_HOB_DATA_
+#define RISCV_SEC_HOB_DATA_
+
+#include <PiPei.h>
+
+#define RISCV_SEC_HANDOFF_HOB_GUID { 0xe5ad277d, 0xc2a2, 0x4462, { 0xb1, 0x60, 0x1e, 0x37, 0x6e, 0xdd, 0xf1, 0x95 } }
+
+typedef struct {
+ UINTN BootHartId;
+ VOID *FdtPointer;
+} RISCV_SEC_HANDOFF_DATA;
+
+#endif /* RISCV_SEC_HOB_DATA_ */
diff --git a/UefiCpuPkg/Include/Library/AmdSvsmLib.h b/UefiCpuPkg/Include/Library/AmdSvsmLib.h index 693b79b..b84c0bb 100644 --- a/UefiCpuPkg/Include/Library/AmdSvsmLib.h +++ b/UefiCpuPkg/Include/Library/AmdSvsmLib.h @@ -139,4 +139,13 @@ AmdSvsmVtpmCmd ( IN OUT UINT8 *Buffer
);
+BOOLEAN
+EFIAPI
+AmdSvsmQueryProtocol (
+ IN UINT32 ProtocolId,
+ IN UINT32 ProtocolVersion,
+ OUT UINT32 *ProtocolMin,
+ OUT UINT32 *ProtocolMax
+ );
+
#endif
diff --git a/UefiCpuPkg/Include/Library/BaseRiscVFpuLib.h b/UefiCpuPkg/Include/Library/BaseRiscVFpuLib.h deleted file mode 100644 index d75320f..0000000 --- a/UefiCpuPkg/Include/Library/BaseRiscVFpuLib.h +++ /dev/null @@ -1,21 +0,0 @@ -/** @file
-
- Copyright (c) 2024, Canonical Services Ltd<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef BASE_RISCV_FPU_LIB_H_
-#define BASE_RISCV_FPU_LIB_H_
-
-/**
- Initialize floating point unit
-
-**/
-EFI_STATUS
-EFIAPI
-RiscVInitializeFpu (
- VOID
- );
-
-#endif /* BASE_RISCV_FPU_LIB_H_ */
diff --git a/UefiCpuPkg/Library/AmdSvsmLibNull/AmdSvsmLibNull.c b/UefiCpuPkg/Library/AmdSvsmLibNull/AmdSvsmLibNull.c index fc6871c..990d640 100644 --- a/UefiCpuPkg/Library/AmdSvsmLibNull/AmdSvsmLibNull.c +++ b/UefiCpuPkg/Library/AmdSvsmLibNull/AmdSvsmLibNull.c @@ -153,3 +153,15 @@ AmdSvsmVtpmCmd ( {
return FALSE;
}
+
+BOOLEAN
+EFIAPI
+AmdSvsmQueryProtocol (
+ IN UINT32 ProtocolId,
+ IN UINT32 ProtocolVersion,
+ OUT UINT32 *ProtocolMin,
+ OUT UINT32 *ProtocolMax
+ )
+{
+ return FALSE;
+}
diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf deleted file mode 100644 index d804629..0000000 --- a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf +++ /dev/null @@ -1,42 +0,0 @@ -## @file
-# RISC-V CPU Exception Handler Library
-#
-# Copyright (c) 2022-2023, Ventana Micro Systems Inc. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001B
- BASE_NAME = BaseRiscV64CpuExceptionHandlerLib
- MODULE_UNI_FILE = BaseRiscV64CpuExceptionHandlerLib.uni
- FILE_GUID = 6AB0D5FD-E615-45A3-9374-E284FB061FC9
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = CpuExceptionHandlerLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV64
-#
-
-[Sources]
- SupervisorTrapHandler.S
- CpuExceptionHandlerLib.c
- CpuExceptionHandlerLib.h
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
-
-[LibraryClasses]
- BaseLib
- SerialPortLib
- PrintLib
- SynchronizationLib
- PeCoffGetEntryPointLib
- MemoryAllocationLib
- DebugLib
diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.uni b/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.uni deleted file mode 100644 index 00cca22..0000000 --- a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.uni +++ /dev/null @@ -1,13 +0,0 @@ -// /** @file
-//
-// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-//
-// SPDX-License-Identifier: BSD-2-Clause-Patent
-//
-// **/
-
-
-#string STR_MODULE_ABSTRACT #language en-US "RISC-V CPU Exception Handler Librarys."
-
-#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU Exception Handler Librarys."
-
diff --git a/UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf b/UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf deleted file mode 100644 index 8130430..0000000 --- a/UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf +++ /dev/null @@ -1,26 +0,0 @@ -## @file
-# RISC-V FPU library.
-#
-# Copyright (c) 2024, Canonical Services Ltd
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001b
- BASE_NAME = BaseRiscVFpuLib
- FILE_GUID = e600fe4d-8595-40f3-90a0-5f043ce155c2
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = RiscVFpuLib
-
-[Sources]
- RiscVFpuCore.S
-
-[Packages]
- MdePkg/MdePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
-
-[LibraryClasses]
- BaseLib
diff --git a/UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S b/UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S deleted file mode 100644 index b439af4..0000000 --- a/UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S +++ /dev/null @@ -1,22 +0,0 @@ -/** @file
-*
-* Copyright (c) 2024, Canonical Services Ltd
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#include <Library/BaseRiscVFpuLib.h>
-#include <Register/RiscV64/RiscVImpl.h>
-
-//
-// Initialize floating point unit
-//
-ASM_FUNC (RiscVInitializeFpu)
- csrr a0, CSR_SSTATUS
- li a1, MSTATUS_FS
- or a0, a0, a1
- csrw CSR_SSTATUS, a0
- csrw CSR_FCSR, x0
- li a0, 0
- ret
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf index 9fcba00..9e0b54e 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf @@ -19,7 +19,7 @@ #
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 LOONGARCH64
+# VALID_ARCHITECTURES = IA32 X64 LOONGARCH64 RISCV64
#
[Sources.Ia32]
@@ -46,6 +46,14 @@ LoongArch/LoongArch64/ArchExceptionHandler.c
LoongArch/LoongArch64/ExceptionHandlerAsm.S | GCC
+[Sources.RISCV64]
+ RiscV/Backtrace.h
+ RiscV/Backtrace.c
+ RiscV/BacktraceHelper.c
+ RiscV/ExceptionLib.c
+ RiscV/ExceptionHandler.h
+ RiscV/ExceptionHandlerAsm.S | GCC
+
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
@@ -75,5 +83,8 @@ [LibraryClasses.LoongArch64]
CpuLib
+[Guids.RISCV64]
+ gEfiDebugImageInfoTableGuid
+
[BuildOptions]
XCODE:*_*_X64_NASM_FLAGS = -D NO_ABSOLUTE_RELOCS_IN_TEXT
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/Backtrace.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/Backtrace.c new file mode 100644 index 0000000..9765d72 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/Backtrace.c @@ -0,0 +1,175 @@ +/** @file
+ RISC-V backtrace implementation.
+
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2025, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Backtrace.h"
+
+#define MAX_STACK_FRAME_SIZE SIZE_16KB
+
+STATIC
+INTN
+CheckFpValid (
+ IN UINTN Fp,
+ IN UINTN Sp
+ )
+{
+ UINTN Low, High;
+
+ Low = Sp + 2 * sizeof (UINTN);
+ High = ALIGN_VALUE (Sp, MAX_STACK_FRAME_SIZE);
+
+ return !(Fp < Low || Fp > High || Fp & 0x07);
+}
+
+STATIC
+CONST CHAR8 *
+BaseName (
+ IN CONST CHAR8 *FullName
+ )
+{
+ CONST CHAR8 *Str;
+
+ Str = FullName + AsciiStrLen (FullName);
+
+ while (--Str > FullName) {
+ if ((*Str == '/') || (*Str == '\\')) {
+ return Str + 1;
+ }
+ }
+
+ return Str;
+}
+
+/**
+ Helper for displaying a backtrace.
+
+ @param Regs Pointer to SMODE_TRAP_REGISTERS.
+ @param FirstPdb Pointer to the first symbol file used.
+ @param ListImage If true, only show the full path to symbol file, else
+ show the PC value and its decoded components.
+**/
+STATIC
+VOID
+DumpCpuBacktraceHelper (
+ IN SMODE_TRAP_REGISTERS *Regs,
+ IN CHAR8 *FirstPdb,
+ IN BOOLEAN ListImage
+ )
+{
+ UINTN ImageBase;
+ UINTN PeCoffSizeOfHeader;
+ BOOLEAN IsLeaf;
+ UINTN RootFp;
+ UINTN RootRa;
+ UINTN Sp;
+ UINTN Fp;
+ UINTN Ra;
+ UINTN Idx;
+ CHAR8 *Pdb;
+ CHAR8 *PrevPdb;
+
+ RootRa = Regs->ra;
+ RootFp = Regs->s0;
+
+ Idx = 0;
+ IsLeaf = TRUE;
+ Fp = RootFp;
+ Ra = RootRa;
+ PrevPdb = FirstPdb;
+ while (Fp != 0) {
+ Pdb = GetImageName (Ra, &ImageBase, &PeCoffSizeOfHeader);
+ if (Pdb != NULL) {
+ if (Pdb != PrevPdb) {
+ Idx++;
+ if (ListImage) {
+ DEBUG ((DEBUG_ERROR, "[% 2d] %a\n", Idx, Pdb));
+ }
+
+ PrevPdb = Pdb;
+ }
+
+ if (!ListImage) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "PC 0x%012lx (0x%012lx+0x%08x) [% 2d] %a\n",
+ Ra,
+ ImageBase,
+ Ra - ImageBase,
+ Idx,
+ BaseName (Pdb)
+ ));
+ }
+ } else if (!ListImage) {
+ DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", Ra));
+ }
+
+ /*
+ * After the prologue, the frame pointer register s0 will point
+ * to the Canonical Frame Address or CFA, which is the stack
+ * pointer value on entry to the current procedure. The previous
+ * frame pointer and return address pair will reside just prior
+ * to the current stack address held in s0. This puts the return
+ * address at s0 - XLEN/8, and the previous frame pointer at
+ * s0 - 2 * XLEN/8.
+ */
+ Sp = Fp;
+ Fp -= sizeof (UINTN) * 2;
+ Ra = *(UINTN *)(Fp + sizeof (UINTN));
+ Fp = *(UINTN *)(Fp);
+ if (IsLeaf && CheckFpValid (Ra, Sp)) {
+ /* We hit function where ra is not saved on the stack */
+ Fp = Ra;
+ Ra = RootRa;
+ }
+
+ IsLeaf = FALSE;
+ }
+}
+
+/**
+ Display a backtrace.
+
+ @param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+EFIAPI
+DumpCpuBacktrace (
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ SMODE_TRAP_REGISTERS *Regs;
+ CHAR8 *Pdb;
+ UINTN ImageBase;
+ UINTN PeCoffSizeOfHeader;
+
+ Regs = (SMODE_TRAP_REGISTERS *)SystemContext.SystemContextRiscV64;
+ Pdb = GetImageName (Regs->sepc, &ImageBase, &PeCoffSizeOfHeader);
+ if (Pdb != NULL) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "PC 0x%012lx (0x%012lx+0x%08x) [ 0] %a\n",
+ Regs->sepc,
+ ImageBase,
+ Regs->sepc - ImageBase,
+ BaseName (Pdb)
+ ));
+ } else {
+ DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", Regs->sepc));
+ }
+
+ DumpCpuBacktraceHelper (Regs, Pdb, FALSE);
+
+ if (Pdb != NULL) {
+ DEBUG ((DEBUG_ERROR, "\n[ 0] %a\n", Pdb));
+ }
+
+ DumpCpuBacktraceHelper (Regs, Pdb, TRUE);
+}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/Backtrace.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/Backtrace.h new file mode 100644 index 0000000..6e29b90 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/Backtrace.h @@ -0,0 +1,57 @@ +/** @file
+
+ RISC-V backtrace definition file.
+
+ Copyright (c) 2025, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef BACKTRACE_H_
+#define BACKTRACE_H_
+
+#include <PiPei.h>
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PeCoffExtraActionLib.h>
+#include <Library/PeCoffGetEntryPointLib.h>
+#include <Library/UefiLib.h>
+#include <Guid/DebugImageInfoTable.h>
+#include "ExceptionHandler.h"
+
+/**
+ Use the EFI Debug Image Table to lookup the FaultAddress and find which PE/COFF image
+ it came from. As long as the PE/COFF image contains a debug directory entry a
+ string can be returned. For ELF and Mach-O images the string points to the Mach-O or ELF
+ image. Microsoft tools contain a pointer to the PDB file that contains the debug information.
+
+ @param FaultAddress Address to find PE/COFF image for.
+ @param ImageBase Return load address of found image
+ @param PeCoffSizeOfHeaders Return the size of the PE/COFF header for the image that was found
+
+ @retval NULL FaultAddress not in a loaded PE/COFF image.
+ @retval Path and file name of PE/COFF image.
+
+**/
+CHAR8 *
+EFIAPI
+GetImageName (
+ IN UINTN FaultAddress,
+ OUT UINTN *ImageBase,
+ OUT UINTN *PeCoffSizeOfHeaders
+ );
+
+/**
+ Display a backtrace.
+
+ @param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+EFIAPI
+DumpCpuBacktrace (
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ );
+
+#endif // BACKTRACE_H_
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/BacktraceHelper.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/BacktraceHelper.c new file mode 100644 index 0000000..fdc5666 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/BacktraceHelper.c @@ -0,0 +1,71 @@ +/** @file
+ RISC-V backtrace helper functions.
+
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2025, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Backtrace.h"
+
+/**
+ Use the EFI Debug Image Table to lookup the FaultAddress and find which PE/COFF image
+ it came from. As long as the PE/COFF image contains a debug directory entry a
+ string can be returned. For ELF and Mach-O images the string points to the Mach-O or ELF
+ image. Microsoft tools contain a pointer to the PDB file that contains the debug information.
+
+ @param FaultAddress Address to find PE/COFF image for.
+ @param ImageBase Return load address of found image
+ @param PeCoffSizeOfHeaders Return the size of the PE/COFF header for the image that was found
+
+ @retval NULL FaultAddress not in a loaded PE/COFF image.
+ @retval Path and file name of PE/COFF image.
+
+**/
+CHAR8 *
+EFIAPI
+GetImageName (
+ IN UINTN FaultAddress,
+ OUT UINTN *ImageBase,
+ OUT UINTN *PeCoffSizeOfHeaders
+ )
+{
+ EFI_STATUS Status;
+ EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *DebugTableHeader;
+ EFI_DEBUG_IMAGE_INFO *DebugTable;
+ UINTN Entry;
+ CHAR8 *Address;
+
+ Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&DebugTableHeader);
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ DebugTable = DebugTableHeader->EfiDebugImageInfoTable;
+ if (DebugTable == NULL) {
+ return NULL;
+ }
+
+ Address = (CHAR8 *)(UINTN)FaultAddress;
+ for (Entry = 0; Entry < DebugTableHeader->TableSize; Entry++, DebugTable++) {
+ if (DebugTable->NormalImage != NULL) {
+ if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) &&
+ (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL))
+ {
+ if ((Address >= (CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase) &&
+ (Address <= ((CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase + DebugTable->NormalImage->LoadedImageProtocolInstance->ImageSize)))
+ {
+ *ImageBase = (UINTN)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;
+ *PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)*ImageBase);
+ return PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase);
+ }
+ }
+ }
+ }
+
+ return NULL;
+}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/BacktraceHelperSec.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/BacktraceHelperSec.c new file mode 100644 index 0000000..10e3497 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/BacktraceHelperSec.c @@ -0,0 +1,42 @@ +/** @file
+ RISC-V backtrace helper functions for SEC.
+
+ Copyright (c) 2025, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Backtrace.h"
+
+/**
+ Use the EFI Debug Image Table to lookup the FaultAddress and find which PE/COFF image
+ it came from. As long as the PE/COFF image contains a debug directory entry a
+ string can be returned. For ELF and Mach-O images the string points to the Mach-O or ELF
+ image. Microsoft tools contain a pointer to the PDB file that contains the debug information.
+
+ @param FaultAddress Address to find PE/COFF image for.
+ @param ImageBase Return load address of found image
+ @param PeCoffSizeOfHeaders Return the size of the PE/COFF header for the image that was found
+
+ @retval NULL FaultAddress not in a loaded PE/COFF image.
+ @retval Path and file name of PE/COFF image.
+
+**/
+CHAR8 *
+EFIAPI
+GetImageName (
+ IN UINTN FaultAddress,
+ OUT UINTN *ImageBase,
+ OUT UINTN *PeCoffSizeOfHeaders
+ )
+{
+ //
+ // This function is not implemented in SEC phase.
+ // It should be implemented in DXE phase.
+ //
+ *ImageBase = 0;
+ *PeCoffSizeOfHeaders = 0;
+
+ return NULL;
+}
diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/ExceptionHandler.h index 9b7e130..0cf8221 100644 --- a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/ExceptionHandler.h @@ -8,16 +8,16 @@ **/
-#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_
-#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_
+#ifndef EXCEPTION_HANDLER_H_
+#define EXCEPTION_HANDLER_H_
#include <Register/RiscV64/RiscVImpl.h>
/**
Trap Handler for S-mode
-
**/
VOID
+EFIAPI
SupervisorModeTrap (
VOID
);
@@ -108,4 +108,4 @@ typedef struct { } SMODE_TRAP_REGISTERS;
#pragma pack()
-#endif
+#endif /* EXCEPTION_HANDLER_H_ */
diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHandler.S b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/ExceptionHandlerAsm.S index 45070b5..815e28b 100644 --- a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHandler.S +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/ExceptionHandlerAsm.S @@ -8,7 +8,7 @@ **/
#include <Base.h>
-#include "CpuExceptionHandlerLib.h"
+#include "ExceptionHandler.h"
.align 3
.section .entry, "ax", %progbits
diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/ExceptionLib.c index 73a9dd5..d19c992 100644 --- a/UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV/ExceptionLib.c @@ -2,6 +2,9 @@ RISC-V Exception Handler library implementation.
Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2025, Ventana Micro Systems Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -14,7 +17,8 @@ #include <Library/SerialPortLib.h>
#include <Library/PrintLib.h>
#include <Register/RiscV64/RiscVEncoding.h>
-#include "CpuExceptionHandlerLib.h"
+#include "Backtrace.h"
+#include "ExceptionHandler.h"
//
// Define the maximum message length
@@ -136,11 +140,21 @@ DumpCpuContext ( )
{
UINTN Printed;
+ UINTN RecursiveException;
SMODE_TRAP_REGISTERS *Regs;
Printed = 0;
Regs = (SMODE_TRAP_REGISTERS *)SystemContext.SystemContextRiscV64;
+ RecursiveException = RiscVGetSupervisorScratch ();
+ if (RecursiveException == 0xdeaddead) {
+ InternalPrintMessage ("\nRecursive exception occurred while dumping the CPU state\n");
+
+ CpuDeadLoop ();
+ }
+
+ RiscVSetSupervisorScratch ((UINTN)0xdeaddead);
+
InternalPrintMessage (
"!!!! RISCV64 Exception Type - %016x(%a) !!!!\n",
ExceptionType,
@@ -171,6 +185,8 @@ DumpCpuContext ( #undef REG
#undef REGS
+ DumpCpuBacktrace (SystemContext);
+
DEBUG_CODE_END ();
}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf index 64de252..00a5b49 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf @@ -20,7 +20,7 @@ # The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
-# VALID_ARCHITECTURES = IA32 X64 LOONGARCH64
+# VALID_ARCHITECTURES = IA32 X64 LOONGARCH64 RISCV64
#
[Sources.Ia32]
@@ -46,6 +46,13 @@ LoongArch/LoongArch64/ArchExceptionHandler.c
LoongArch/LoongArch64/ExceptionHandlerAsm.S | GCC
+[Sources.RISCV64]
+ RiscV/Backtrace.h
+ RiscV/Backtrace.c
+ RiscV/BacktraceHelperSec.c
+ RiscV/ExceptionLib.c
+ RiscV/ExceptionHandler.h
+ RiscV/ExceptionHandlerAsm.S | GCC
[Packages]
MdePkg/MdePkg.dec
diff --git a/UefiCpuPkg/Library/MpInitLib/AmdSev.c b/UefiCpuPkg/Library/MpInitLib/AmdSev.c index 5108873..8ffb1b5 100644 --- a/UefiCpuPkg/Library/MpInitLib/AmdSev.c +++ b/UefiCpuPkg/Library/MpInitLib/AmdSev.c @@ -273,7 +273,7 @@ SevEsPlaceApHlt ( @param[in] ExchangeInfo The pointer to CPU Exchange Data structure
**/
VOID
-FillExchangeInfoDataSevEs (
+FillExchangeInfoDataSevSnp (
IN volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo
)
{
@@ -293,8 +293,6 @@ FillExchangeInfoDataSevEs ( );
ExchangeInfo->ExtTopoAvail = !!ExtTopoEbx.Bits.LogicalProcessors;
}
-
- ExchangeInfo->SevSnpKnownInitApicId = FALSE;
}
/**
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index 96c0980..63b8464 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -1018,15 +1018,17 @@ FillExchangeInfoData ( ExchangeInfo->Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
DEBUG ((DEBUG_INFO, "%a: 5-Level Paging = %d\n", gEfiCallerBaseName, ExchangeInfo->Enable5LevelPaging));
- ExchangeInfo->SevEsIsEnabled = CpuMpData->SevEsIsEnabled;
- ExchangeInfo->SevSnpIsEnabled = CpuMpData->SevSnpIsEnabled;
- ExchangeInfo->GhcbBase = (UINTN)CpuMpData->GhcbBase;
+ ExchangeInfo->SevEsIsEnabled = CpuMpData->SevEsIsEnabled;
+ ExchangeInfo->SevSnpIsEnabled = CpuMpData->SevSnpIsEnabled;
+ ExchangeInfo->GhcbBase = (UINTN)CpuMpData->GhcbBase;
+ ExchangeInfo->ExtTopoAvail = FALSE;
+ ExchangeInfo->SevSnpKnownInitApicId = FALSE;
//
- // Populate SEV-ES specific exchange data.
+ // Populate SEV-SNP specific exchange data.
//
if (ExchangeInfo->SevSnpIsEnabled) {
- FillExchangeInfoDataSevEs (ExchangeInfo);
+ FillExchangeInfoDataSevSnp (ExchangeInfo);
}
//
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h index 60cae3b..5d10516 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -901,7 +901,7 @@ ConfidentialComputingGuestHas ( @param[in] ExchangeInfo The pointer to CPU Exchange Data structure
**/
VOID
-FillExchangeInfoDataSevEs (
+FillExchangeInfoDataSevSnp (
IN volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo
);
diff --git a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm b/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm index 66d63a2..64358e5 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm @@ -24,13 +24,6 @@ ;
SevSnpGetInitCpuNumber:
;
- ; If not an SNP guest, leave EBX (CpuNumber) as is
- ;
- lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevSnpIsEnabled)]
- cmp byte [edi], 1 ; SevSnpIsEnabled
- jne SevSnpGetCpuNumberDone
-
- ;
; If not starting the AP with a specific ApicId, leave EBX (CpuNumber) as is
;
lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevSnpKnownInitApicId)]
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index 7402a28..1d53b78 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -236,12 +236,14 @@ SmmWaitForApArrival ( UINTN Index;
UINT32 DelayedCount;
UINT32 BlockedCount;
+ UINT32 DisabledCount;
BOOLEAN SyncNeeded;
PERF_FUNCTION_BEGIN ();
- DelayedCount = 0;
- BlockedCount = 0;
+ DelayedCount = 0;
+ BlockedCount = 0;
+ DisabledCount = 0;
ASSERT (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SyncContext) <= mNumberOfCpus);
@@ -318,12 +320,13 @@ SmmWaitForApArrival ( }
}
+ mSmmMpSyncData->AllApArrivedWithException = AllCpusInSmmExceptBlockedDisabled ();
if (!mSmmMpSyncData->AllApArrivedWithException) {
//
- // Check for the Blocked & Delayed Case.
+ // Check for the Disabled & Blocked & Delayed Case.
//
- GetSmmDelayedBlockedDisabledCount (&DelayedCount, &BlockedCount, NULL);
- DEBUG ((DEBUG_INFO, "SmmWaitForApArrival: Delayed AP Count = %d, Blocked AP Count = %d\n", DelayedCount, BlockedCount));
+ GetSmmDelayedBlockedDisabledCount (&DelayedCount, &BlockedCount, &DisabledCount);
+ DEBUG ((DEBUG_ERROR, "SmmWaitForApArrival: Failed to wait all APs enter SMI. Delayed AP Count = %d, Blocked AP Count = %d, Disabled AP Count = %d\n", DelayedCount, BlockedCount, DisabledCount));
}
PERF_FUNCTION_END ();
diff --git a/UefiCpuPkg/SecCore/SecBist.c b/UefiCpuPkg/SecCore/SecBist.c index cd2e340..5016f37 100644 --- a/UefiCpuPkg/SecCore/SecBist.c +++ b/UefiCpuPkg/SecCore/SecBist.c @@ -8,6 +8,45 @@ #include "SecMain.h"
+/**
+ Implementation of the PlatformInformation service in EFI_SEC_PLATFORM_INFORMATION_PPI.
+
+ @param PeiServices Pointer to the PEI Services Table.
+ @param StructureSize Pointer to the variable describing size of the input buffer.
+ @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformationBist (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
+ );
+
+/**
+ Implementation of the PlatformInformation2 service in EFI_SEC_PLATFORM_INFORMATION2_PPI.
+
+ @param PeiServices The pointer to the PEI Services Table.
+ @param StructureSize The pointer to the variable describing size of the input buffer.
+ @param PlatformInformationRecord2 The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD2.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small. The current buffer size needed to
+ hold the record is returned in StructureSize.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation2Bist (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2
+ );
+
EFI_SEC_PLATFORM_INFORMATION_PPI mSecPlatformInformation = {
SecPlatformInformationBist
};
diff --git a/UefiCpuPkg/SecCore/SecCore.inf b/UefiCpuPkg/SecCore/SecCore.inf index 94966f4..255d3a9 100644 --- a/UefiCpuPkg/SecCore/SecCore.inf +++ b/UefiCpuPkg/SecCore/SecCore.inf @@ -31,11 +31,14 @@ SecMain.c
SecMain.h
FindPeiCore.c
- SecBist.c
[Sources.IA32]
Ia32/ResetVec.nasmb
+[Sources.IA32, Sources.X64]
+ SecBist.c
+ SecTemporaryRamDone.c
+
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
@@ -55,9 +58,11 @@ PeiServicesLib
PeiServicesTablePointerLib
HobLib
- CpuPageTableLib
StackCheckLib
+[LibraryClasses.IA32, LibraryClasses.X64]
+ CpuPageTableLib
+
[Ppis]
## SOMETIMES_CONSUMES
## PRODUCES
diff --git a/UefiCpuPkg/SecCore/SecCoreNative.inf b/UefiCpuPkg/SecCore/SecCoreNative.inf index facb79c..4d9f385 100644 --- a/UefiCpuPkg/SecCore/SecCoreNative.inf +++ b/UefiCpuPkg/SecCore/SecCoreNative.inf @@ -31,7 +31,10 @@ SecMain.c
SecMain.h
FindPeiCore.c
+
+[Sources.IA32, Sources.X64]
SecBist.c
+ SecTemporaryRamDone.c
[Packages]
MdePkg/MdePkg.dec
@@ -52,9 +55,11 @@ PeiServicesLib
PeiServicesTablePointerLib
HobLib
- CpuPageTableLib
StackCheckLib
+[LibraryClasses.IA32, LibraryClasses.X64]
+ CpuPageTableLib
+
[Ppis]
## SOMETIMES_CONSUMES
## PRODUCES
diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c index 23a75d3..f6917e8 100644 --- a/UefiCpuPkg/SecCore/SecMain.c +++ b/UefiCpuPkg/SecCore/SecMain.c @@ -2,12 +2,48 @@ C functions in SEC
Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2025, Ventana Micro Systems Inc. All rights reserved.<BR>
+
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "SecMain.h"
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+
+#define SEC_IDT_ENTRY_COUNT 34
+
+typedef struct _SEC_IDT_TABLE {
+ //
+ // Reserved 8 bytes preceding IDT to store EFI_PEI_SERVICES**, since IDT base
+ // address should be 8-byte alignment.
+ // Note: For IA32, only the 4 bytes immediately preceding IDT is used to store
+ // EFI_PEI_SERVICES**
+ //
+ UINT64 PeiService;
+ IA32_IDT_GATE_DESCRIPTOR IdtTable[SEC_IDT_ENTRY_COUNT];
+} SEC_IDT_TABLE;
+
+//
+// These are IDT entries pointing to 10:FFFFFFE4h.
+//
+UINT64 mIdtEntryTemplate = 0xffff8e000010ffe4ULL;
+
+/**
+ TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked
+ by the PEI Foundation after the EFI_PEI_PERMANANT_MEMORY_INSTALLED_PPI is installed.
+
+ @retval EFI_SUCCESS Use of Temporary RAM was disabled.
+ @retval EFI_INVALID_PARAMETER Temporary RAM could not be disabled.
+
+**/
+EFI_STATUS
+EFIAPI
+SecTemporaryRamDone (
+ VOID
+ );
+
EFI_PEI_TEMPORARY_RAM_DONE_PPI gSecTemporaryRamDonePpi = {
SecTemporaryRamDone
};
@@ -34,136 +70,18 @@ EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = { &mSecPlatformInformationPpi
}
};
-
-/**
- Migrates the Global Descriptor Table (GDT) to permanent memory.
-
- @retval EFI_SUCCESS The GDT was migrated successfully.
- @retval EFI_OUT_OF_RESOURCES The GDT could not be migrated due to lack of available memory.
-
-**/
-EFI_STATUS
-MigrateGdt (
- VOID
- )
-{
- EFI_STATUS Status;
- UINTN GdtBufferSize;
- IA32_DESCRIPTOR Gdtr;
- VOID *GdtBuffer;
-
- AsmReadGdtr ((IA32_DESCRIPTOR *)&Gdtr);
- GdtBufferSize = sizeof (IA32_SEGMENT_DESCRIPTOR) -1 + Gdtr.Limit + 1;
-
- Status = PeiServicesAllocatePool (
- GdtBufferSize,
- &GdtBuffer
- );
- ASSERT (GdtBuffer != NULL);
- if (EFI_ERROR (Status)) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- GdtBuffer = ALIGN_POINTER (GdtBuffer, sizeof (IA32_SEGMENT_DESCRIPTOR));
- CopyMem (GdtBuffer, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
- Gdtr.Base = (UINTN)GdtBuffer;
- AsmWriteGdtr (&Gdtr);
-
- return EFI_SUCCESS;
-}
-
-/**
- Get Paging Mode
-
- @retval Paging Mode.
-**/
-PAGING_MODE
-GetPagingMode (
- VOID
- )
-{
- IA32_CR4 Cr4;
- BOOLEAN Page5LevelSupport;
- UINT32 RegEax;
- CPUID_EXTENDED_CPU_SIG_EDX RegEdx;
- BOOLEAN Page1GSupport;
- PAGING_MODE PagingMode;
-
- //
- // Check Page5Level Support or not.
- //
- Cr4.UintN = AsmReadCr4 ();
- Page5LevelSupport = (Cr4.Bits.LA57 ? TRUE : FALSE);
-
- //
- // Check Page1G Support or not.
- //
- Page1GSupport = FALSE;
- AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
- if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
- AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx.Uint32);
- if (RegEdx.Bits.Page1GB != 0) {
- Page1GSupport = TRUE;
- }
- }
-
- //
- // Decide Paging Mode according Page5LevelSupport & Page1GSupport.
- //
- if (Page5LevelSupport) {
- PagingMode = Page1GSupport ? Paging5Level1GB : Paging5Level;
- } else {
- PagingMode = Page1GSupport ? Paging4Level1GB : Paging4Level;
- }
-
- return PagingMode;
-}
-
-/**
- Get max physical address supported by specific page mode
-
- @param[in] PagingMode The paging mode.
-
- @retval Max Address.
-**/
-UINT32
-GetMaxAddress (
- IN PAGING_MODE PagingMode
- )
-{
- CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
- UINT32 MaxExtendedFunctionId;
- UINT32 MaxAddressBits;
-
- VirPhyAddressSize.Uint32 = 0;
-
- //
- // Get Maximum Physical Address Bits
- // Get the number of address lines; Maximum Physical Address is 2^PhysicalAddressBits - 1.
- // If CPUID does not supported, then use a max value of 36 as per SDM 3A, 4.1.4.
- //
- AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunctionId, NULL, NULL, NULL);
- if (MaxExtendedFunctionId >= CPUID_VIR_PHY_ADDRESS_SIZE) {
- AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);
- MaxAddressBits = VirPhyAddressSize.Bits.PhysicalAddressBits;
- } else {
- MaxAddressBits = 36;
- }
-
- if ((PagingMode == Paging4Level1GB) || (PagingMode == Paging4Level)) {
+#else
+EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = {
+ {
//
- // The max liner address bits is 48 for 4 level page table.
+ // SecPerformance PPI notify descriptor.
//
- MaxAddressBits = MIN (VirPhyAddressSize.Bits.PhysicalAddressBits, 48);
+ EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,
+ &gPeiSecPerformancePpiGuid,
+ (VOID *)(UINTN)SecPerformancePpiCallBack
}
-
- return MaxAddressBits;
-}
-
-//
-// These are IDT entries pointing to 10:FFFFFFE4h.
-//
-UINT64 mIdtEntryTemplate = 0xffff8e000010ffe4ULL;
+};
+#endif
/**
Caller provided function to be invoked at the end of InitializeDebugAgent().
@@ -241,9 +159,6 @@ SecStartup ( )
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
- IA32_DESCRIPTOR IdtDescriptor;
- SEC_IDT_TABLE IdtTableInStack;
- UINT32 Index;
UINT32 PeiStackSize;
EFI_STATUS Status;
@@ -282,6 +197,11 @@ SecStartup ( //
InitializeFloatingPointUnits ();
+ #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+ IA32_DESCRIPTOR IdtDescriptor;
+ SEC_IDT_TABLE IdtTableInStack;
+ UINT32 Index;
+
// |-------------------|---->
// |IDT Table |
// |-------------------|
@@ -307,6 +227,7 @@ SecStartup ( IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);
AsmWriteIdtr (&IdtDescriptor);
+ #endif
//
// Setup the default exception handlers
@@ -520,179 +441,3 @@ SecStartupPhase2 ( //
UNREACHABLE ();
}
-
-/**
- TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked
- by the PEI Foundation after the EFI_PEI_PERMANANT_MEMORY_INSTALLED_PPI is installed.
-
- @retval EFI_SUCCESS Use of Temporary RAM was disabled.
- @retval EFI_INVALID_PARAMETER Temporary RAM could not be disabled.
-
-**/
-EFI_STATUS
-EFIAPI
-SecTemporaryRamDone (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_STATUS Status2;
- UINTN Index;
- BOOLEAN State;
- EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor;
- REPUBLISH_SEC_PPI_PPI *RepublishSecPpiPpi;
- IA32_CR0 Cr0;
- PAGING_MODE PagingMode;
- UINT32 MaxAddressBits;
- UINTN PageTable;
- EFI_PHYSICAL_ADDRESS Buffer;
- UINTN BufferSize;
- UINT64 Length;
- UINT64 Address;
- IA32_MAP_ATTRIBUTE MapAttribute;
- IA32_MAP_ATTRIBUTE MapMask;
-
- PageTable = 0;
- BufferSize = 0;
- MapAttribute.Uint64 = 0;
- MapAttribute.Bits.Present = 1;
- MapAttribute.Bits.ReadWrite = 1;
- MapMask.Uint64 = MAX_UINT64;
-
- //
- // Republish Sec Platform Information(2) PPI
- //
- RepublishSecPlatformInformationPpi ();
-
- //
- // Re-install SEC PPIs using a PEIM produced service if published
- //
- for (Index = 0, Status = EFI_SUCCESS; Status == EFI_SUCCESS; Index++) {
- Status = PeiServicesLocatePpi (
- &gRepublishSecPpiPpiGuid,
- Index,
- &PeiPpiDescriptor,
- (VOID **)&RepublishSecPpiPpi
- );
- if (!EFI_ERROR (Status)) {
- DEBUG ((DEBUG_INFO, "Calling RepublishSecPpi instance %d.\n", Index));
- Status2 = RepublishSecPpiPpi->RepublishSecPpis ();
- ASSERT_EFI_ERROR (Status2);
- }
- }
-
- //
- // Migrate DebugAgentContext.
- //
- InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
-
- //
- // Disable interrupts and save current interrupt state
- //
- State = SaveAndDisableInterrupts ();
-
- //
- // Migrate GDT before NEM near down
- //
- if (PcdGetBool (PcdMigrateTemporaryRamFirmwareVolumes)) {
- Status = MigrateGdt ();
- ASSERT_EFI_ERROR (Status);
- }
-
- //
- // Migrate page table to permanent memory mapping entire physical address space if CR0.PG is set.
- //
- Cr0.UintN = AsmReadCr0 ();
- if (Cr0.Bits.PG != 0) {
- //
- // Assume CPU runs in 64bit mode if paging is enabled.
- //
- ASSERT (sizeof (UINTN) == sizeof (UINT64));
-
- //
- // Get PagingMode & MaxAddressBits.
- //
- PagingMode = GetPagingMode ();
- MaxAddressBits = GetMaxAddress (PagingMode);
- DEBUG ((DEBUG_INFO, "SecTemporaryRamDone: PagingMode = 0x%lx, MaxAddressBits = %d\n", PagingMode, MaxAddressBits));
-
- //
- // Create page table to cover the max mapping address in physical memory before Temp
- // Ram Exit. The max mapping address is defined by PcdMaxMappingAddressBeforeTempRamExit.
- //
- Length = FixedPcdGet64 (PcdMaxMappingAddressBeforeTempRamExit);
- Length = MIN (LShiftU64 (1, MaxAddressBits), Length);
- if (Length != 0) {
- Status = PageTableMap (&PageTable, PagingMode, 0, &BufferSize, 0, Length, &MapAttribute, &MapMask, NULL);
- ASSERT (Status == EFI_BUFFER_TOO_SMALL);
- if (Status != EFI_BUFFER_TOO_SMALL) {
- return Status;
- }
-
- Status = PeiServicesAllocatePages (
- EfiBootServicesData,
- EFI_SIZE_TO_PAGES (BufferSize),
- &Buffer
- );
- if (EFI_ERROR (Status)) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- Status = PageTableMap (&PageTable, PagingMode, (VOID *)(UINTN)Buffer, &BufferSize, 0, Length, &MapAttribute, &MapMask, NULL);
- ASSERT (BufferSize == 0);
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "SecTemporaryRamDone: Failed to create page table in physical memory before Temp Ram Exit: %r.\n", Status));
- CpuDeadLoop ();
- }
-
- AsmWriteCr3 (PageTable);
- }
- }
-
- //
- // Disable Temporary RAM after Stack and Heap have been migrated at this point.
- //
- SecPlatformDisableTemporaryMemory ();
-
- //
- // Expanding the page table to cover the entire memory space since the physical memory is WB after TempRamExit.
- //
- if ((Cr0.Bits.PG != 0) && (Length < LShiftU64 (1, MaxAddressBits))) {
- Address = Length;
- Length = LShiftU64 (1, MaxAddressBits) - Length;
-
- MapAttribute.Uint64 = Address;
- MapAttribute.Bits.Present = 1;
- MapAttribute.Bits.ReadWrite = 1;
-
- Status = PageTableMap (&PageTable, PagingMode, 0, &BufferSize, Address, Length, &MapAttribute, &MapMask, NULL);
- ASSERT (Status == EFI_BUFFER_TOO_SMALL);
- if (Status != EFI_BUFFER_TOO_SMALL) {
- return Status;
- }
-
- Status = PeiServicesAllocatePages (
- EfiBootServicesData,
- EFI_SIZE_TO_PAGES (BufferSize),
- &Buffer
- );
- if (EFI_ERROR (Status)) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- Status = PageTableMap (&PageTable, PagingMode, (VOID *)(UINTN)Buffer, &BufferSize, Address, Length, &MapAttribute, &MapMask, NULL);
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "SecTemporaryRamDone: Failed to create full range page table in physical memory after Temp Ram Exit: %r.\n", Status));
- CpuDeadLoop ();
- }
-
- AsmWriteCr3 (PageTable);
- }
-
- //
- // Restore original interrupt state
- //
- SetInterruptState (State);
-
- return EFI_SUCCESS;
-}
diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h index 81c5614..6b312a8 100644 --- a/UefiCpuPkg/SecCore/SecMain.h +++ b/UefiCpuPkg/SecCore/SecMain.h @@ -33,36 +33,6 @@ #include <Library/PeiServicesTablePointerLib.h>
#include <Library/HobLib.h>
#include <Library/PeiServicesLib.h>
-#include <Library/CpuPageTableLib.h>
-#include <Register/Intel/Cpuid.h>
-#include <Register/Intel/Msr.h>
-
-#define SEC_IDT_ENTRY_COUNT 34
-
-typedef struct _SEC_IDT_TABLE {
- //
- // Reserved 8 bytes preceding IDT to store EFI_PEI_SERVICES**, since IDT base
- // address should be 8-byte alignment.
- // Note: For IA32, only the 4 bytes immediately preceding IDT is used to store
- // EFI_PEI_SERVICES**
- //
- UINT64 PeiService;
- IA32_IDT_GATE_DESCRIPTOR IdtTable[SEC_IDT_ENTRY_COUNT];
-} SEC_IDT_TABLE;
-
-/**
- TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked
- by the PEI Foundation after the EFI_PEI_PERMANANT_MEMORY_INSTALLED_PPI is installed.
-
- @retval EFI_SUCCESS Use of Temporary RAM was disabled.
- @retval EFI_INVALID_PARAMETER Temporary RAM could not be disabled.
-
-**/
-EFI_STATUS
-EFIAPI
-SecTemporaryRamDone (
- VOID
- );
/**
Entry point to the C language phase of SEC. After the SEC assembly
@@ -102,45 +72,6 @@ FindAndReportEntryPoints ( );
/**
- Implementation of the PlatformInformation service in EFI_SEC_PLATFORM_INFORMATION_PPI.
-
- @param PeiServices Pointer to the PEI Services Table.
- @param StructureSize Pointer to the variable describing size of the input buffer.
- @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
-
-**/
-EFI_STATUS
-EFIAPI
-SecPlatformInformationBist (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN OUT UINT64 *StructureSize,
- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
- );
-
-/**
- Implementation of the PlatformInformation2 service in EFI_SEC_PLATFORM_INFORMATION2_PPI.
-
- @param PeiServices The pointer to the PEI Services Table.
- @param StructureSize The pointer to the variable describing size of the input buffer.
- @param PlatformInformationRecord2 The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD2.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_BUFFER_TOO_SMALL The buffer was too small. The current buffer size needed to
- hold the record is returned in StructureSize.
-
-**/
-EFI_STATUS
-EFIAPI
-SecPlatformInformation2Bist (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN OUT UINT64 *StructureSize,
- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2
- );
-
-/**
Republish SecPlatformInformationPpi/SecPlatformInformation2Ppi.
**/
diff --git a/UefiCpuPkg/SecCore/SecTemporaryRamDone.c b/UefiCpuPkg/SecCore/SecTemporaryRamDone.c new file mode 100644 index 0000000..f921d45 --- /dev/null +++ b/UefiCpuPkg/SecCore/SecTemporaryRamDone.c @@ -0,0 +1,315 @@ +/** @file
+ SEC platform information(2) PPI.
+
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2025, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/CpuPageTableLib.h>
+#include <Register/Intel/Cpuid.h>
+#include <Register/Intel/Msr.h>
+#include "SecMain.h"
+
+/**
+ Migrates the Global Descriptor Table (GDT) to permanent memory.
+
+ @retval EFI_SUCCESS The GDT was migrated successfully.
+ @retval EFI_OUT_OF_RESOURCES The GDT could not be migrated due to lack of available memory.
+
+**/
+EFI_STATUS
+MigrateGdt (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN GdtBufferSize;
+ IA32_DESCRIPTOR Gdtr;
+ VOID *GdtBuffer;
+
+ AsmReadGdtr ((IA32_DESCRIPTOR *)&Gdtr);
+ GdtBufferSize = sizeof (IA32_SEGMENT_DESCRIPTOR) -1 + Gdtr.Limit + 1;
+
+ Status = PeiServicesAllocatePool (
+ GdtBufferSize,
+ &GdtBuffer
+ );
+ ASSERT (GdtBuffer != NULL);
+ if (EFI_ERROR (Status)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ GdtBuffer = ALIGN_POINTER (GdtBuffer, sizeof (IA32_SEGMENT_DESCRIPTOR));
+ CopyMem (GdtBuffer, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
+ Gdtr.Base = (UINTN)GdtBuffer;
+ AsmWriteGdtr (&Gdtr);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Get Paging Mode
+
+ @retval Paging Mode.
+**/
+PAGING_MODE
+GetPagingMode (
+ VOID
+ )
+{
+ IA32_CR4 Cr4;
+ BOOLEAN Page5LevelSupport;
+ UINT32 RegEax;
+ CPUID_EXTENDED_CPU_SIG_EDX RegEdx;
+ BOOLEAN Page1GSupport;
+ PAGING_MODE PagingMode;
+
+ //
+ // Check Page5Level Support or not.
+ //
+ Cr4.UintN = AsmReadCr4 ();
+ Page5LevelSupport = (Cr4.Bits.LA57 ? TRUE : FALSE);
+
+ //
+ // Check Page1G Support or not.
+ //
+ Page1GSupport = FALSE;
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
+ if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
+ AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx.Uint32);
+ if (RegEdx.Bits.Page1GB != 0) {
+ Page1GSupport = TRUE;
+ }
+ }
+
+ //
+ // Decide Paging Mode according Page5LevelSupport & Page1GSupport.
+ //
+ if (Page5LevelSupport) {
+ PagingMode = Page1GSupport ? Paging5Level1GB : Paging5Level;
+ } else {
+ PagingMode = Page1GSupport ? Paging4Level1GB : Paging4Level;
+ }
+
+ return PagingMode;
+}
+
+/**
+ Get max physical address supported by specific page mode
+
+ @param[in] PagingMode The paging mode.
+
+ @retval Max Address.
+**/
+UINT32
+GetMaxAddress (
+ IN PAGING_MODE PagingMode
+ )
+{
+ CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
+ UINT32 MaxExtendedFunctionId;
+ UINT32 MaxAddressBits;
+
+ VirPhyAddressSize.Uint32 = 0;
+
+ //
+ // Get Maximum Physical Address Bits
+ // Get the number of address lines; Maximum Physical Address is 2^PhysicalAddressBits - 1.
+ // If CPUID does not supported, then use a max value of 36 as per SDM 3A, 4.1.4.
+ //
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunctionId, NULL, NULL, NULL);
+ if (MaxExtendedFunctionId >= CPUID_VIR_PHY_ADDRESS_SIZE) {
+ AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);
+ MaxAddressBits = VirPhyAddressSize.Bits.PhysicalAddressBits;
+ } else {
+ MaxAddressBits = 36;
+ }
+
+ if ((PagingMode == Paging4Level1GB) || (PagingMode == Paging4Level)) {
+ //
+ // The max liner address bits is 48 for 4 level page table.
+ //
+ MaxAddressBits = MIN (VirPhyAddressSize.Bits.PhysicalAddressBits, 48);
+ }
+
+ return MaxAddressBits;
+}
+
+/**
+ TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked
+ by the PEI Foundation after the EFI_PEI_PERMANANT_MEMORY_INSTALLED_PPI is installed.
+
+ @retval EFI_SUCCESS Use of Temporary RAM was disabled.
+ @retval EFI_INVALID_PARAMETER Temporary RAM could not be disabled.
+
+**/
+EFI_STATUS
+EFIAPI
+SecTemporaryRamDone (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_STATUS Status2;
+ UINTN Index;
+ BOOLEAN State;
+ EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor;
+ REPUBLISH_SEC_PPI_PPI *RepublishSecPpiPpi;
+ IA32_CR0 Cr0;
+ PAGING_MODE PagingMode;
+ UINT32 MaxAddressBits;
+ UINTN PageTable;
+ EFI_PHYSICAL_ADDRESS Buffer;
+ UINTN BufferSize;
+ UINT64 Length;
+ UINT64 Address;
+ IA32_MAP_ATTRIBUTE MapAttribute;
+ IA32_MAP_ATTRIBUTE MapMask;
+
+ PageTable = 0;
+ BufferSize = 0;
+ MapAttribute.Uint64 = 0;
+ MapAttribute.Bits.Present = 1;
+ MapAttribute.Bits.ReadWrite = 1;
+ MapMask.Uint64 = MAX_UINT64;
+
+ //
+ // Republish Sec Platform Information(2) PPI
+ //
+ RepublishSecPlatformInformationPpi ();
+
+ //
+ // Re-install SEC PPIs using a PEIM produced service if published
+ //
+ for (Index = 0, Status = EFI_SUCCESS; Status == EFI_SUCCESS; Index++) {
+ Status = PeiServicesLocatePpi (
+ &gRepublishSecPpiPpiGuid,
+ Index,
+ &PeiPpiDescriptor,
+ (VOID **)&RepublishSecPpiPpi
+ );
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "Calling RepublishSecPpi instance %d.\n", Index));
+ Status2 = RepublishSecPpiPpi->RepublishSecPpis ();
+ ASSERT_EFI_ERROR (Status2);
+ }
+ }
+
+ //
+ // Migrate DebugAgentContext.
+ //
+ InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
+
+ //
+ // Disable interrupts and save current interrupt state
+ //
+ State = SaveAndDisableInterrupts ();
+
+ //
+ // Migrate GDT before NEM near down
+ //
+ if (PcdGetBool (PcdMigrateTemporaryRamFirmwareVolumes)) {
+ Status = MigrateGdt ();
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ //
+ // Migrate page table to permanent memory mapping entire physical address space if CR0.PG is set.
+ //
+ Cr0.UintN = AsmReadCr0 ();
+ if (Cr0.Bits.PG != 0) {
+ //
+ // Assume CPU runs in 64bit mode if paging is enabled.
+ //
+ ASSERT (sizeof (UINTN) == sizeof (UINT64));
+
+ //
+ // Get PagingMode & MaxAddressBits.
+ //
+ PagingMode = GetPagingMode ();
+ MaxAddressBits = GetMaxAddress (PagingMode);
+ DEBUG ((DEBUG_INFO, "SecTemporaryRamDone: PagingMode = 0x%lx, MaxAddressBits = %d\n", PagingMode, MaxAddressBits));
+
+ //
+ // Create page table to cover the max mapping address in physical memory before Temp
+ // Ram Exit. The max mapping address is defined by PcdMaxMappingAddressBeforeTempRamExit.
+ //
+ Length = FixedPcdGet64 (PcdMaxMappingAddressBeforeTempRamExit);
+ Length = MIN (LShiftU64 (1, MaxAddressBits), Length);
+ if (Length != 0) {
+ Status = PageTableMap (&PageTable, PagingMode, 0, &BufferSize, 0, Length, &MapAttribute, &MapMask, NULL);
+ ASSERT (Status == EFI_BUFFER_TOO_SMALL);
+ if (Status != EFI_BUFFER_TOO_SMALL) {
+ return Status;
+ }
+
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesData,
+ EFI_SIZE_TO_PAGES (BufferSize),
+ &Buffer
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Status = PageTableMap (&PageTable, PagingMode, (VOID *)(UINTN)Buffer, &BufferSize, 0, Length, &MapAttribute, &MapMask, NULL);
+ ASSERT (BufferSize == 0);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "SecTemporaryRamDone: Failed to create page table in physical memory before Temp Ram Exit: %r.\n", Status));
+ CpuDeadLoop ();
+ }
+
+ AsmWriteCr3 (PageTable);
+ }
+ }
+
+ //
+ // Disable Temporary RAM after Stack and Heap have been migrated at this point.
+ //
+ SecPlatformDisableTemporaryMemory ();
+
+ //
+ // Expanding the page table to cover the entire memory space since the physical memory is WB after TempRamExit.
+ //
+ if ((Cr0.Bits.PG != 0) && (Length < LShiftU64 (1, MaxAddressBits))) {
+ Address = Length;
+ Length = LShiftU64 (1, MaxAddressBits) - Length;
+
+ MapAttribute.Uint64 = Address;
+ MapAttribute.Bits.Present = 1;
+ MapAttribute.Bits.ReadWrite = 1;
+
+ Status = PageTableMap (&PageTable, PagingMode, 0, &BufferSize, Address, Length, &MapAttribute, &MapMask, NULL);
+ ASSERT (Status == EFI_BUFFER_TOO_SMALL);
+ if (Status != EFI_BUFFER_TOO_SMALL) {
+ return Status;
+ }
+
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesData,
+ EFI_SIZE_TO_PAGES (BufferSize),
+ &Buffer
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Status = PageTableMap (&PageTable, PagingMode, (VOID *)(UINTN)Buffer, &BufferSize, Address, Length, &MapAttribute, &MapMask, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "SecTemporaryRamDone: Failed to create full range page table in physical memory after Temp Ram Exit: %r.\n", Status));
+ CpuDeadLoop ();
+ }
+
+ AsmWriteCr3 (PageTable);
+ }
+
+ //
+ // Restore original interrupt state
+ //
+ SetInterruptState (State);
+
+ return EFI_SUCCESS;
+}
diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml b/UefiCpuPkg/UefiCpuPkg.ci.yaml index a6fd147..57867dd 100644 --- a/UefiCpuPkg/UefiCpuPkg.ci.yaml +++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml @@ -30,7 +30,6 @@ ],
## Both file path and directory path are accepted.
"IgnoreFiles": [
- "Library/BaseRiscV64CpuExceptionHandlerLib/CpuExceptionHandlerLib.h"
]
},
"CompilerPlugin": {
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 8164c59..3789ee9 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -80,8 +80,6 @@ SmmRelocationLib|Include/Library/SmmRelocationLib.h
[LibraryClasses.RISCV64]
- ## @libraryclass Provides function to initialize the FPU.
- RiscVFpuLib|Include/Library/BaseRiscVFpuLib.h
## @libraryclass Provides functions to manage MMU features on RISCV64 CPUs.
##
RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 4503536..e011b18 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -218,9 +218,7 @@ UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHandlerLibUnitTest.inf
[Components.RISCV64]
- UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
- UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf
UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
|