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-rw-r--r--UefiCpuPkg/SecCore/SecMain.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index e9e243c..173bbfc 100644
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -281,7 +281,7 @@ SecStartupPhase2(
// will be built based on them in PEI phase.
//
SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);
- SecCoreData->PeiTemporaryRamSize &= ~0x07;
+ SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;
} else {
//
// No addition PPI, PpiList directly point to the common PPI list.