diff options
Diffstat (limited to 'MdeModulePkg/Bus/Pci/XhciDxe')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c | 19 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h | 2 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c | 243 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h | 63 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 866 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h | 193 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 197 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 356 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 1270 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h | 1148 |
10 files changed, 2204 insertions, 2153 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c b/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c index 9e2697b..e3af49c 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.c @@ -21,15 +21,15 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gXhciComponentName = //
// EFI Component Name 2 Protocol
//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2 = {
- (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) XhciComponentNameGetDriverName,
- (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) XhciComponentNameGetControllerName,
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)XhciComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)XhciComponentNameGetControllerName,
"en"
};
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mXhciDriverNameTable[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mXhciDriverNameTable[] = {
{ "eng;en", L"Usb Xhci Driver" },
- { NULL , NULL }
+ { NULL, NULL }
};
/**
@@ -166,9 +166,9 @@ XhciComponentNameGetControllerName ( OUT CHAR16 **ControllerName
)
{
- EFI_STATUS Status;
- EFI_USB2_HC_PROTOCOL *Usb2Hc;
- USB_XHCI_INSTANCE *XhciDev;
+ EFI_STATUS Status;
+ EFI_USB2_HC_PROTOCOL *Usb2Hc;
+ USB_XHCI_INSTANCE *XhciDev;
//
// This is a device driver, so ChildHandle must be NULL.
@@ -195,7 +195,7 @@ XhciComponentNameGetControllerName ( Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiUsb2HcProtocolGuid,
- (VOID **) &Usb2Hc,
+ (VOID **)&Usb2Hc,
gXhciDriverBinding.DriverBindingHandle,
ControllerHandle,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -213,5 +213,4 @@ XhciComponentNameGetControllerName ( ControllerName,
(BOOLEAN)(This == &gXhciComponentName)
);
-
}
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h b/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h index 13fbde1..103ad60 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/ComponentName.h @@ -57,7 +57,6 @@ XhciComponentNameGetDriverName ( OUT CHAR16 **DriverName
);
-
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
@@ -137,4 +136,3 @@ XhciComponentNameGetControllerName ( );
#endif
-
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c index 005820e..99fb352 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c @@ -7,10 +7,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
-
#include "Xhci.h"
-
/**
Allocate a block of memory to be used by the buffer pool.
@@ -22,17 +20,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Pages
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Pages
)
{
- USBHC_MEM_BLOCK *Block;
- EFI_PCI_IO_PROTOCOL *PciIo;
- VOID *BufHost;
- VOID *Mapping;
- EFI_PHYSICAL_ADDRESS MappedAddr;
- UINTN Bytes;
- EFI_STATUS Status;
+ USBHC_MEM_BLOCK *Block;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ VOID *BufHost;
+ VOID *Mapping;
+ EFI_PHYSICAL_ADDRESS MappedAddr;
+ UINTN Bytes;
+ EFI_STATUS Status;
PciIo = Pool->PciIo;
@@ -47,9 +45,9 @@ UsbHcAllocMemBlock ( //
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
- Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
- Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
- Block->Bits = AllocateZeroPool (Block->BitsLen);
+ Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
+ Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
+ Block->Bits = AllocateZeroPool (Block->BitsLen);
if (Block->Bits == NULL) {
gBS->FreePool (Block);
@@ -73,7 +71,7 @@ UsbHcAllocMemBlock ( goto FREE_BITARRAY;
}
- Bytes = EFI_PAGES_TO_SIZE (Pages);
+ Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
@@ -87,9 +85,9 @@ UsbHcAllocMemBlock ( goto FREE_BUFFER;
}
- Block->BufHost = BufHost;
- Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
- Block->Mapping = Mapping;
+ Block->BufHost = BufHost;
+ Block->Buf = (UINT8 *)((UINTN)MappedAddr);
+ Block->Mapping = Mapping;
return Block;
@@ -102,7 +100,6 @@ FREE_BITARRAY: return NULL;
}
-
/**
Free the memory block from the memory pool.
@@ -112,11 +109,11 @@ FREE_BITARRAY: **/
VOID
UsbHcFreeMemBlock (
- IN USBHC_MEM_POOL *Pool,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_POOL *Pool,
+ IN USBHC_MEM_BLOCK *Block
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -132,7 +129,6 @@ UsbHcFreeMemBlock ( gBS->FreePool (Block);
}
-
/**
Alloc some memory from the block.
@@ -145,22 +141,22 @@ UsbHcFreeMemBlock ( **/
VOID *
UsbHcAllocMemFromBlock (
- IN USBHC_MEM_BLOCK *Block,
- IN UINTN Units
+ IN USBHC_MEM_BLOCK *Block,
+ IN UINTN Units
)
{
- UINTN Byte;
- UINT8 Bit;
- UINTN StartByte;
- UINT8 StartBit;
- UINTN Available;
- UINTN Count;
+ UINTN Byte;
+ UINT8 Bit;
+ UINTN StartByte;
+ UINT8 StartBit;
+ UINTN Available;
+ UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
- StartByte = 0;
- StartBit = 0;
- Available = 0;
+ StartByte = 0;
+ StartBit = 0;
+ Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -176,13 +172,12 @@ UsbHcAllocMemFromBlock ( }
NEXT_BIT (Byte, Bit);
-
} else {
NEXT_BIT (Byte, Bit);
- Available = 0;
- StartByte = Byte;
- StartBit = Bit;
+ Available = 0;
+ StartByte = Byte;
+ StartBit = Bit;
}
}
@@ -193,13 +188,13 @@ UsbHcAllocMemFromBlock ( //
// Mark the memory as allocated
//
- Byte = StartByte;
- Bit = StartBit;
+ Byte = StartByte;
+ Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -218,16 +213,16 @@ UsbHcAllocMemFromBlock ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINTN AllocSize;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINTN Offset;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINTN AllocSize;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -241,7 +236,7 @@ UsbHcGetPciAddrForHostAddr ( // scan the memory block list for the memory block that
// completely contains the allocated memory.
//
- if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
+ if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -250,8 +245,8 @@ UsbHcGetPciAddrForHostAddr ( //
// calculate the pci memory address for host memory address.
//
- Offset = (UINT8 *)Mem - Block->BufHost;
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
+ Offset = (UINT8 *)Mem - Block->BufHost;
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
@@ -267,16 +262,16 @@ UsbHcGetPciAddrForHostAddr ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINTN AllocSize;
- EFI_PHYSICAL_ADDRESS HostAddr;
- UINTN Offset;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINTN AllocSize;
+ EFI_PHYSICAL_ADDRESS HostAddr;
+ UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -290,7 +285,7 @@ UsbHcGetHostAddrForPciAddr ( // scan the memory block list for the memory block that
// completely contains the allocated memory.
//
- if ((Block->Buf <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
+ if ((Block->Buf <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->Buf + Block->BufLen))) {
break;
}
}
@@ -299,8 +294,8 @@ UsbHcGetHostAddrForPciAddr ( //
// calculate the pci memory address for host memory address.
//
- Offset = (UINT8 *)Mem - Block->Buf;
- HostAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->BufHost + Offset);
+ Offset = (UINT8 *)Mem - Block->Buf;
+ HostAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->BufHost + Offset);
return HostAddr;
}
@@ -313,8 +308,8 @@ UsbHcGetHostAddrForPciAddr ( **/
VOID
UsbHcInsertMemBlockToPool (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -322,7 +317,6 @@ UsbHcInsertMemBlockToPool ( Head->Next = Block;
}
-
/**
Is the memory block empty?
@@ -334,10 +328,10 @@ UsbHcInsertMemBlockToPool ( **/
BOOLEAN
UsbHcIsMemBlockEmpty (
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Block
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -348,7 +342,6 @@ UsbHcIsMemBlockEmpty ( return TRUE;
}
-
/**
Unlink the memory block from the pool's list.
@@ -358,11 +351,11 @@ UsbHcIsMemBlockEmpty ( **/
VOID
UsbHcUnlinkMemBlock (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *BlockToUnlink
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *BlockToUnlink
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT ((Head != NULL) && (BlockToUnlink != NULL));
@@ -375,7 +368,6 @@ UsbHcUnlinkMemBlock ( }
}
-
/**
Initialize the memory management pool for the host controller.
@@ -390,7 +382,7 @@ UsbHcInitMemPool ( IN EFI_PCI_IO_PROTOCOL *PciIo
)
{
- USBHC_MEM_POOL *Pool;
+ USBHC_MEM_POOL *Pool;
Pool = AllocatePool (sizeof (USBHC_MEM_POOL));
@@ -398,8 +390,8 @@ UsbHcInitMemPool ( return Pool;
}
- Pool->PciIo = PciIo;
- Pool->Head = UsbHcAllocMemBlock (Pool, USBHC_MEM_DEFAULT_PAGES);
+ Pool->PciIo = PciIo;
+ Pool->Head = UsbHcAllocMemBlock (Pool, USBHC_MEM_DEFAULT_PAGES);
if (Pool->Head == NULL) {
gBS->FreePool (Pool);
@@ -409,7 +401,6 @@ UsbHcInitMemPool ( return Pool;
}
-
/**
Release the memory management pool.
@@ -421,10 +412,10 @@ UsbHcInitMemPool ( **/
EFI_STATUS
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -443,7 +434,6 @@ UsbHcFreeMemPool ( return EFI_SUCCESS;
}
-
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -456,16 +446,16 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- USBHC_MEM_BLOCK *NewBlock;
- VOID *Mem;
- UINTN AllocSize;
- UINTN Pages;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *NewBlock;
+ VOID *Mem;
+ UINTN AllocSize;
+ UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -520,7 +510,6 @@ UsbHcAllocateMem ( return Mem;
}
-
/**
Free the allocated memory back to the memory pool.
@@ -531,22 +520,22 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINT8 *ToFree;
- UINTN AllocSize;
- UINTN Byte;
- UINTN Bit;
- UINTN Count;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINT8 *ToFree;
+ UINTN AllocSize;
+ UINTN Byte;
+ UINTN Bit;
+ UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
- ToFree = (UINT8 *) Mem;
+ ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -557,8 +546,8 @@ UsbHcFreeMem ( //
// compute the start byte and bit in the bit array
//
- Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
- Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
+ Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8;
+ Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -566,7 +555,7 @@ UsbHcFreeMem ( for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -589,7 +578,7 @@ UsbHcFreeMem ( UsbHcFreeMemBlock (Pool, Block);
}
- return ;
+ return;
}
/**
@@ -621,13 +610,13 @@ UsbHcAllocateAlignedPages ( OUT VOID **Mapping
)
{
- EFI_STATUS Status;
- VOID *Memory;
- UINTN AlignedMemory;
- UINTN AlignmentMask;
- UINTN UnalignedPages;
- UINTN RealPages;
- UINTN Bytes;
+ EFI_STATUS Status;
+ VOID *Memory;
+ UINTN AlignedMemory;
+ UINTN AlignmentMask;
+ UINTN UnalignedPages;
+ UINTN RealPages;
+ UINTN Bytes;
//
// Alignment must be a power of two or zero.
@@ -641,12 +630,13 @@ UsbHcAllocateAlignedPages ( if (Pages == 0) {
return EFI_INVALID_PARAMETER;
}
+
if (Alignment > EFI_PAGE_SIZE) {
//
// Calculate the total number of pages since alignment is larger than page size.
//
- AlignmentMask = Alignment - 1;
- RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
+ AlignmentMask = Alignment - 1;
+ RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
//
// Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
//
@@ -663,8 +653,9 @@ UsbHcAllocateAlignedPages ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
- UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);
+
+ AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;
+ UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);
if (UnalignedPages > 0) {
//
// Free first unaligned page(s).
@@ -672,6 +663,7 @@ UsbHcAllocateAlignedPages ( Status = PciIo->FreeBuffer (PciIo, UnalignedPages, Memory);
ASSERT_EFI_ERROR (Status);
}
+
Memory = (VOID *)(UINTN)(AlignedMemory + EFI_PAGES_TO_SIZE (Pages));
UnalignedPages = RealPages - Pages - UnalignedPages;
if (UnalignedPages > 0) {
@@ -696,25 +688,26 @@ UsbHcAllocateAlignedPages ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- AlignedMemory = (UINTN) Memory;
+
+ AlignedMemory = (UINTN)Memory;
}
- Bytes = EFI_PAGES_TO_SIZE (Pages);
+ Bytes = EFI_PAGES_TO_SIZE (Pages);
Status = PciIo->Map (
PciIo,
EfiPciIoOperationBusMasterCommonBuffer,
- (VOID *) AlignedMemory,
+ (VOID *)AlignedMemory,
&Bytes,
DeviceAddress,
Mapping
);
if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) {
- Status = PciIo->FreeBuffer (PciIo, Pages, (VOID *) AlignedMemory);
+ Status = PciIo->FreeBuffer (PciIo, Pages, (VOID *)AlignedMemory);
return EFI_OUT_OF_RESOURCES;
}
- *HostAddress = (VOID *) AlignedMemory;
+ *HostAddress = (VOID *)AlignedMemory;
return EFI_SUCCESS;
}
@@ -730,13 +723,13 @@ UsbHcAllocateAlignedPages ( **/
VOID
UsbHcFreeAlignedPages (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN VOID *HostAddress,
- IN UINTN Pages,
- VOID *Mapping
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN VOID *HostAddress,
+ IN UINTN Pages,
+ VOID *Mapping
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Pages != 0);
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h index 319110d..48ae861 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h @@ -10,20 +10,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_XHCI_MEM_H_
#define _EFI_XHCI_MEM_H_
-#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
+#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
- UINT8 *Bits; // Bit array to record which unit is allocated
- UINTN BitsLen;
- UINT8 *Buf;
- UINT8 *BufHost;
- UINTN BufLen; // Memory size in bytes
- VOID *Mapping;
- USBHC_MEM_BLOCK *Next;
+ UINT8 *Bits; // Bit array to record which unit is allocated
+ UINTN BitsLen;
+ UINT8 *Buf;
+ UINT8 *BufHost;
+ UINTN BufLen; // Memory size in bytes
+ VOID *Mapping;
+ USBHC_MEM_BLOCK *Next;
};
//
@@ -32,16 +32,16 @@ struct _USBHC_MEM_BLOCK { // data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
- EFI_PCI_IO_PROTOCOL *PciIo;
- BOOLEAN Check4G;
- UINT32 Which4G;
- USBHC_MEM_BLOCK *Head;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ BOOLEAN Check4G;
+ UINT32 Which4G;
+ USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
-#define USBHC_MEM_UNIT 64
+#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
@@ -60,8 +60,6 @@ typedef struct _USBHC_MEM_POOL { } \
} while (0)
-
-
/**
Initialize the memory management pool for the host controller.
@@ -76,7 +74,6 @@ UsbHcInitMemPool ( IN EFI_PCI_IO_PROTOCOL *PciIo
);
-
/**
Release the memory management pool.
@@ -88,10 +85,9 @@ UsbHcInitMemPool ( **/
EFI_STATUS
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
);
-
/**
Allocate some memory from the host controller's memory pool
which can be used to communicate with host controller.
@@ -104,11 +100,10 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
);
-
/**
Free the allocated memory back to the memory pool.
@@ -119,9 +114,9 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -136,9 +131,9 @@ UsbHcFreeMem ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddrForHostAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -153,9 +148,9 @@ UsbHcGetPciAddrForHostAddr ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetHostAddrForPciAddr (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
/**
@@ -198,10 +193,10 @@ UsbHcAllocateAlignedPages ( **/
VOID
UsbHcFreeAlignedPages (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN VOID *HostAddress,
- IN UINTN Pages,
- VOID *Mapping
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN VOID *HostAddress,
+ IN UINTN Pages,
+ VOID *Mapping
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c index 5a1f907..b79499e 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c @@ -13,46 +13,46 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // to the UEFI protocol's port state (change).
//
USB_PORT_STATE_MAP mUsbPortStateMap[] = {
- {XHC_PORTSC_CCS, USB_PORT_STAT_CONNECTION},
- {XHC_PORTSC_PED, USB_PORT_STAT_ENABLE},
- {XHC_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},
- {XHC_PORTSC_RESET, USB_PORT_STAT_RESET}
+ { XHC_PORTSC_CCS, USB_PORT_STAT_CONNECTION },
+ { XHC_PORTSC_PED, USB_PORT_STAT_ENABLE },
+ { XHC_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT },
+ { XHC_PORTSC_RESET, USB_PORT_STAT_RESET }
};
USB_PORT_STATE_MAP mUsbPortChangeMap[] = {
- {XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},
- {XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},
- {XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},
- {XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET}
+ { XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION },
+ { XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE },
+ { XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT },
+ { XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET }
};
-USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {
- {XHC_PORTSC_CSC, EfiUsbPortConnectChange},
- {XHC_PORTSC_PEC, EfiUsbPortEnableChange},
- {XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange},
- {XHC_PORTSC_PRC, EfiUsbPortResetChange}
+USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {
+ { XHC_PORTSC_CSC, EfiUsbPortConnectChange },
+ { XHC_PORTSC_PEC, EfiUsbPortEnableChange },
+ { XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange },
+ { XHC_PORTSC_PRC, EfiUsbPortResetChange }
};
USB_PORT_STATE_MAP mUsbHubPortStateMap[] = {
- {XHC_HUB_PORTSC_CCS, USB_PORT_STAT_CONNECTION},
- {XHC_HUB_PORTSC_PED, USB_PORT_STAT_ENABLE},
- {XHC_HUB_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},
- {XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET}
+ { XHC_HUB_PORTSC_CCS, USB_PORT_STAT_CONNECTION },
+ { XHC_HUB_PORTSC_PED, USB_PORT_STAT_ENABLE },
+ { XHC_HUB_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT },
+ { XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET }
};
USB_PORT_STATE_MAP mUsbHubPortChangeMap[] = {
- {XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},
- {XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},
- {XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},
- {XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET}
+ { XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION },
+ { XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE },
+ { XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT },
+ { XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET }
};
-USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {
- {XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange},
- {XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange},
- {XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange},
- {XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange},
- {XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange}
+USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {
+ { XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange },
+ { XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange },
+ { XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange },
+ { XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange },
+ { XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange }
};
EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding = {
@@ -67,7 +67,7 @@ EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding = { //
// Template for Xhci's Usb2 Host Controller Protocol Instance.
//
-EFI_USB2_HC_PROTOCOL gXhciUsb2HcTemplate = {
+EFI_USB2_HC_PROTOCOL gXhciUsb2HcTemplate = {
XhcGetCapability,
XhcReset,
XhcGetState,
@@ -114,12 +114,12 @@ XhcGetCapability ( return EFI_INVALID_PARAMETER;
}
- OldTpl = gBS->RaiseTPL (XHC_TPL);
+ OldTpl = gBS->RaiseTPL (XHC_TPL);
Xhc = XHC_FROM_THIS (This);
*MaxSpeed = EFI_USB_SPEED_SUPER;
- *PortNumber = (UINT8) (Xhc->HcSParams1.Data.MaxPorts);
- *Is64BitCapable = (UINT8) Xhc->Support64BitDma;
+ *PortNumber = (UINT8)(Xhc->HcSParams1.Data.MaxPorts);
+ *Is64BitCapable = (UINT8)Xhc->Support64BitDma;
DEBUG ((DEBUG_INFO, "XhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));
gBS->RestoreTPL (OldTpl);
@@ -127,7 +127,6 @@ XhcGetCapability ( return EFI_SUCCESS;
}
-
/**
Provides software reset for the USB host controller.
@@ -168,51 +167,54 @@ XhcReset ( OldTpl = gBS->RaiseTPL (XHC_TPL);
switch (Attributes) {
- case EFI_USB_HC_RESET_GLOBAL:
- //
- // Flow through, same behavior as Host Controller Reset
- //
- case EFI_USB_HC_RESET_HOST_CONTROLLER:
- if ((Xhc->DebugCapSupOffset != 0xFFFFFFFF) && ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&
- ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0)) {
- Status = EFI_SUCCESS;
- goto ON_EXIT;
- }
+ case EFI_USB_HC_RESET_GLOBAL:
//
- // Host Controller must be Halt when Reset it
+ // Flow through, same behavior as Host Controller Reset
//
- if (!XhcIsHalt (Xhc)) {
- Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
+ case EFI_USB_HC_RESET_HOST_CONTROLLER:
+ if ((Xhc->DebugCapSupOffset != 0xFFFFFFFF) && ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&
+ ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0))
+ {
+ Status = EFI_SUCCESS;
+ goto ON_EXIT;
+ }
+
+ //
+ // Host Controller must be Halt when Reset it
+ //
+ if (!XhcIsHalt (Xhc)) {
+ Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
+
+ if (EFI_ERROR (Status)) {
+ Status = EFI_DEVICE_ERROR;
+ goto ON_EXIT;
+ }
+ }
+
+ Status = XhcResetHC (Xhc, XHC_RESET_TIMEOUT);
+ ASSERT (!(XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_CNR)));
if (EFI_ERROR (Status)) {
- Status = EFI_DEVICE_ERROR;
goto ON_EXIT;
}
- }
-
- Status = XhcResetHC (Xhc, XHC_RESET_TIMEOUT);
- ASSERT (!(XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_CNR)));
- if (EFI_ERROR (Status)) {
- goto ON_EXIT;
- }
- //
- // Clean up the asynchronous transfers, currently only
- // interrupt supports asynchronous operation.
- //
- XhciDelAllAsyncIntTransfers (Xhc);
- XhcFreeSched (Xhc);
+ //
+ // Clean up the asynchronous transfers, currently only
+ // interrupt supports asynchronous operation.
+ //
+ XhciDelAllAsyncIntTransfers (Xhc);
+ XhcFreeSched (Xhc);
- XhcInitSched (Xhc);
- break;
+ XhcInitSched (Xhc);
+ break;
- case EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG:
- case EFI_USB_HC_RESET_HOST_WITH_DEBUG:
- Status = EFI_UNSUPPORTED;
- break;
+ case EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG:
+ case EFI_USB_HC_RESET_HOST_WITH_DEBUG:
+ Status = EFI_UNSUPPORTED;
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
ON_EXIT:
@@ -222,7 +224,6 @@ ON_EXIT: return Status;
}
-
/**
Retrieve the current state of the USB host controller.
@@ -252,7 +253,7 @@ XhcGetState ( OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
if (XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
*State = EfiUsbHcStateHalt;
@@ -285,10 +286,10 @@ XhcSetState ( IN EFI_USB_HC_STATE State
)
{
- USB_XHCI_INSTANCE *Xhc;
- EFI_STATUS Status;
- EFI_USB_HC_STATE CurState;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ EFI_STATUS Status;
+ EFI_USB_HC_STATE CurState;
+ EFI_TPL OldTpl;
Status = XhcGetState (This, &CurState);
@@ -302,38 +303,38 @@ XhcSetState ( OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
switch (State) {
- case EfiUsbHcStateHalt:
- Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
- break;
-
- case EfiUsbHcStateOperational:
- if (XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE)) {
- Status = EFI_DEVICE_ERROR;
+ case EfiUsbHcStateHalt:
+ Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);
break;
- }
- //
- // Software must not write a one to this field unless the host controller
- // is in the Halted state. Doing so will yield undefined results.
- // refers to Spec[XHCI1.0-2.3.1]
- //
- if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
- Status = EFI_DEVICE_ERROR;
- break;
- }
+ case EfiUsbHcStateOperational:
+ if (XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE)) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
- Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
- break;
+ //
+ // Software must not write a one to this field unless the host controller
+ // is in the Halted state. Doing so will yield undefined results.
+ // refers to Spec[XHCI1.0-2.3.1]
+ //
+ if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
- case EfiUsbHcStateSuspend:
- Status = EFI_UNSUPPORTED;
- break;
+ Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
+ case EfiUsbHcStateSuspend:
+ Status = EFI_UNSUPPORTED;
+ break;
+
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
DEBUG ((DEBUG_INFO, "XhcSetState: status %r\n", Status));
@@ -364,15 +365,15 @@ XhcGetRootHubPortStatus ( OUT EFI_USB_PORT_STATUS *PortStatus
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- UINTN Index;
- UINTN MapSize;
- EFI_STATUS Status;
- USB_DEV_ROUTE ParentRouteChart;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ UINTN Index;
+ UINTN MapSize;
+ EFI_STATUS Status;
+ USB_DEV_ROUTE ParentRouteChart;
+ EFI_TPL OldTpl;
if (PortStatus == NULL) {
return EFI_INVALID_PARAMETER;
@@ -380,8 +381,8 @@ XhcGetRootHubPortStatus ( OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
- Status = EFI_SUCCESS;
+ Xhc = XHC_FROM_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = Xhc->HcSParams1.Data.MaxPorts;
@@ -390,7 +391,7 @@ XhcGetRootHubPortStatus ( goto ON_EXIT;
}
- Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
+ Offset = (UINT32)(XHC_PORTSC_OFFSET + (0x10 * PortNumber));
PortStatus->PortStatus = 0;
PortStatus->PortChangeStatus = 0;
@@ -401,21 +402,21 @@ XhcGetRootHubPortStatus ( // bit 10~13 of the root port status register identifies the speed of the attached device.
//
switch ((State & XHC_PORTSC_PS) >> 10) {
- case 2:
- PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
- break;
+ case 2:
+ PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
+ break;
- case 3:
- PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
- break;
+ case 3:
+ PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
+ break;
- case 4:
- case 5:
- PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;
- break;
+ case 4:
+ case 5:
+ PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;
+ break;
- default:
- break;
+ default:
+ break;
}
//
@@ -425,9 +426,10 @@ XhcGetRootHubPortStatus ( for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {
- PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
+ PortStatus->PortStatus = (UINT16)(PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
}
}
+
//
// Bit5~8 reflects its current link state.
//
@@ -439,7 +441,7 @@ XhcGetRootHubPortStatus ( for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {
- PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
+ PortStatus->PortChangeStatus = (UINT16)(PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
}
}
@@ -463,7 +465,6 @@ ON_EXIT: return Status;
}
-
/**
Sets a feature for the specified root hub port.
@@ -484,12 +485,12 @@ XhcSetRootHubPortFeature ( IN EFI_USB_PORT_FEATURE PortFeature
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
OldTpl = gBS->RaiseTPL (XHC_TPL);
@@ -503,71 +504,71 @@ XhcSetRootHubPortFeature ( goto ON_EXIT;
}
- Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
+ Offset = (UINT32)(XHC_PORTSC_OFFSET + (0x10 * PortNumber));
State = XhcReadOpReg (Xhc, Offset);
//
// Mask off the port status change bits, these bits are
// write clean bit
//
- State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
+ State &= ~(BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
switch (PortFeature) {
- case EfiUsbPortEnable:
- //
- // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
- // A port may be disabled by software writing a '1' to this flag.
- //
- Status = EFI_SUCCESS;
- break;
-
- case EfiUsbPortSuspend:
- State |= XHC_PORTSC_LWS;
- XhcWriteOpReg (Xhc, Offset, State);
- State &= ~XHC_PORTSC_PLS;
- State |= (3 << 5) ;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
-
- case EfiUsbPortReset:
- DEBUG ((DEBUG_INFO, "XhcUsbPortReset!\n"));
- //
- // Make sure Host Controller not halt before reset it
- //
- if (XhcIsHalt (Xhc)) {
- Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
+ case EfiUsbPortEnable:
+ //
+ // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
+ // A port may be disabled by software writing a '1' to this flag.
+ //
+ Status = EFI_SUCCESS;
+ break;
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_INFO, "XhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
- break;
+ case EfiUsbPortSuspend:
+ State |= XHC_PORTSC_LWS;
+ XhcWriteOpReg (Xhc, Offset, State);
+ State &= ~XHC_PORTSC_PLS;
+ State |= (3 << 5);
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
+
+ case EfiUsbPortReset:
+ DEBUG ((DEBUG_INFO, "XhcUsbPortReset!\n"));
+ //
+ // Make sure Host Controller not halt before reset it
+ //
+ if (XhcIsHalt (Xhc)) {
+ Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "XhcSetRootHubPortFeature :failed to start HC - %r\n", Status));
+ break;
+ }
}
- }
- //
- // 4.3.1 Resetting a Root Hub Port
- // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.
- //
- State |= XHC_PORTSC_RESET;
- XhcWriteOpReg (Xhc, Offset, State);
- XhcWaitOpRegBit(Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
- break;
+ //
+ // 4.3.1 Resetting a Root Hub Port
+ // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.
+ //
+ State |= XHC_PORTSC_RESET;
+ XhcWriteOpReg (Xhc, Offset, State);
+ XhcWaitOpRegBit (Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
+ break;
- case EfiUsbPortPower:
- //
- // Not supported, ignore the operation
- //
- Status = EFI_SUCCESS;
- break;
+ case EfiUsbPortPower:
+ //
+ // Not supported, ignore the operation
+ //
+ Status = EFI_SUCCESS;
+ break;
- case EfiUsbPortOwner:
- //
- // XHCI root hub port don't has the owner bit, ignore the operation
- //
- Status = EFI_SUCCESS;
- break;
+ case EfiUsbPortOwner:
+ //
+ // XHCI root hub port don't has the owner bit, ignore the operation
+ //
+ Status = EFI_SUCCESS;
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
ON_EXIT:
@@ -577,7 +578,6 @@ ON_EXIT: return Status;
}
-
/**
Clears a feature for the specified root hub port.
@@ -601,17 +601,17 @@ XhcClearRootHubPortFeature ( IN EFI_USB_PORT_FEATURE PortFeature
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
- Status = EFI_SUCCESS;
+ Xhc = XHC_FROM_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = (Xhc->HcSParams1.Data.MaxPorts);
@@ -627,82 +627,82 @@ XhcClearRootHubPortFeature ( // write clean bit
//
State = XhcReadOpReg (Xhc, Offset);
- State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
+ State &= ~(BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
switch (PortFeature) {
- case EfiUsbPortEnable:
- //
- // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
- // A port may be disabled by software writing a '1' to this flag.
- //
- State |= XHC_PORTSC_PED;
- State &= ~XHC_PORTSC_RESET;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
-
- case EfiUsbPortSuspend:
- State |= XHC_PORTSC_LWS;
- XhcWriteOpReg (Xhc, Offset, State);
- State &= ~XHC_PORTSC_PLS;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
-
- case EfiUsbPortReset:
- //
- // PORTSC_RESET BIT(4) bit is RW1S attribute, which means Write-1-to-set status:
- // Register bits indicate status when read, a clear bit may be set by
- // writing a '1'. Writing a '0' to RW1S bits has no effect.
- //
- break;
+ case EfiUsbPortEnable:
+ //
+ // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
+ // A port may be disabled by software writing a '1' to this flag.
+ //
+ State |= XHC_PORTSC_PED;
+ State &= ~XHC_PORTSC_RESET;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortOwner:
- //
- // XHCI root hub port don't has the owner bit, ignore the operation
- //
- break;
+ case EfiUsbPortSuspend:
+ State |= XHC_PORTSC_LWS;
+ XhcWriteOpReg (Xhc, Offset, State);
+ State &= ~XHC_PORTSC_PLS;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortConnectChange:
- //
- // Clear connect status change
- //
- State |= XHC_PORTSC_CSC;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortReset:
+ //
+ // PORTSC_RESET BIT(4) bit is RW1S attribute, which means Write-1-to-set status:
+ // Register bits indicate status when read, a clear bit may be set by
+ // writing a '1'. Writing a '0' to RW1S bits has no effect.
+ //
+ break;
- case EfiUsbPortEnableChange:
- //
- // Clear enable status change
- //
- State |= XHC_PORTSC_PEC;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortOwner:
+ //
+ // XHCI root hub port don't has the owner bit, ignore the operation
+ //
+ break;
- case EfiUsbPortOverCurrentChange:
- //
- // Clear PortOverCurrent change
- //
- State |= XHC_PORTSC_OCC;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortConnectChange:
+ //
+ // Clear connect status change
+ //
+ State |= XHC_PORTSC_CSC;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortResetChange:
- //
- // Clear Port Reset change
- //
- State |= XHC_PORTSC_PRC;
- XhcWriteOpReg (Xhc, Offset, State);
- break;
+ case EfiUsbPortEnableChange:
+ //
+ // Clear enable status change
+ //
+ State |= XHC_PORTSC_PEC;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- case EfiUsbPortPower:
- case EfiUsbPortSuspendChange:
- //
- // Not supported or not related operation
- //
- break;
+ case EfiUsbPortOverCurrentChange:
+ //
+ // Clear PortOverCurrent change
+ //
+ State |= XHC_PORTSC_OCC;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
- break;
+ case EfiUsbPortResetChange:
+ //
+ // Clear Port Reset change
+ //
+ State |= XHC_PORTSC_PRC;
+ XhcWriteOpReg (Xhc, Offset, State);
+ break;
+
+ case EfiUsbPortPower:
+ case EfiUsbPortSuspendChange:
+ //
+ // Not supported or not related operation
+ //
+ break;
+
+ default:
+ Status = EFI_INVALID_PARAMETER;
+ break;
}
ON_EXIT:
@@ -737,22 +737,22 @@ ON_EXIT: **/
EFI_STATUS
XhcTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 DeviceAddress,
- IN UINT8 EndPointAddress,
- IN UINT8 DeviceSpeed,
- IN UINTN MaximumPacketLength,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN OUT VOID *Data,
- IN OUT UINTN *DataLength,
- IN UINTN Timeout,
- OUT UINT32 *TransferResult
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 DeviceAddress,
+ IN UINT8 EndPointAddress,
+ IN UINT8 DeviceSpeed,
+ IN UINTN MaximumPacketLength,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN OUT VOID *Data,
+ IN OUT UINTN *DataLength,
+ IN UINTN Timeout,
+ OUT UINT32 *TransferResult
)
{
- EFI_STATUS Status;
- EFI_STATUS RecoveryStatus;
- URB *Urb;
+ EFI_STATUS Status;
+ EFI_STATUS RecoveryStatus;
+ URB *Urb;
ASSERT ((Type == XHC_CTRL_TRANSFER) || (Type == XHC_BULK_TRANSFER) || (Type == XHC_INT_TRANSFER_SYNC));
Urb = XhcCreateUrb (
@@ -780,7 +780,7 @@ XhcTransfer ( //
// The transfer timed out. Abort the transfer by dequeueing of the TD.
//
- RecoveryStatus = XhcDequeueTrbFromEndpoint(Xhc, Urb);
+ RecoveryStatus = XhcDequeueTrbFromEndpoint (Xhc, Urb);
if (RecoveryStatus == EFI_ALREADY_STARTED) {
//
// The URB is finished just before stopping endpoint.
@@ -789,8 +789,8 @@ XhcTransfer ( ASSERT (Urb->Result == EFI_USB_NOERROR);
Status = EFI_SUCCESS;
DEBUG ((DEBUG_ERROR, "XhcTransfer[Type=%d]: pending URB is finished, Length = %d.\n", Type, Urb->Completed));
- } else if (EFI_ERROR(RecoveryStatus)) {
- DEBUG((DEBUG_ERROR, "XhcTransfer[Type=%d]: XhcDequeueTrbFromEndpoint failed!\n", Type));
+ } else if (EFI_ERROR (RecoveryStatus)) {
+ DEBUG ((DEBUG_ERROR, "XhcTransfer[Type=%d]: XhcDequeueTrbFromEndpoint failed!\n", Type));
}
}
@@ -799,7 +799,7 @@ XhcTransfer ( if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) {
ASSERT (Status == EFI_DEVICE_ERROR);
- RecoveryStatus = XhcRecoverHaltedEndpoint(Xhc, Urb);
+ RecoveryStatus = XhcRecoverHaltedEndpoint (Xhc, Urb);
if (EFI_ERROR (RecoveryStatus)) {
DEBUG ((DEBUG_ERROR, "XhcTransfer[Type=%d]: XhcRecoverHaltedEndpoint failed!\n", Type));
}
@@ -876,24 +876,28 @@ XhcControlTransfer ( if ((TransferDirection != EfiUsbDataIn) &&
(TransferDirection != EfiUsbDataOut) &&
- (TransferDirection != EfiUsbNoData)) {
+ (TransferDirection != EfiUsbNoData))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection == EfiUsbNoData) &&
- ((Data != NULL) || (*DataLength != 0))) {
+ ((Data != NULL) || (*DataLength != 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection != EfiUsbNoData) &&
- ((Data == NULL) || (*DataLength == 0))) {
+ ((Data == NULL) || (*DataLength == 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&
(MaximumPacketLength != 32) && (MaximumPacketLength != 64) &&
(MaximumPacketLength != 512)
- ) {
+ )
+ {
return EFI_INVALID_PARAMETER;
}
@@ -907,7 +911,7 @@ XhcControlTransfer ( OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
Status = EFI_DEVICE_ERROR;
*TransferResult = EFI_USB_ERR_SYSTEM;
@@ -931,7 +935,8 @@ XhcControlTransfer ( // According to XHCI 1.0 spec, the Set_Address request is replaced by XHCI's Address_Device cmd.
//
if ((Request->Request == USB_REQ_SET_ADDRESS) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)))
+ {
//
// Reset the BusDevAddr field of all disabled entries in UsbDevContext array firstly.
// This way is used to clean the history to avoid using wrong device address by XhcAsyncInterruptTransfer().
@@ -939,7 +944,8 @@ XhcControlTransfer ( for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId == 0) &&
- (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8)Request->Value)) {
+ (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8)Request->Value))
+ {
Xhc->UsbDevContext[Index + 1].BusDevAddr = 0;
}
}
@@ -948,6 +954,7 @@ XhcControlTransfer ( Status = EFI_DEVICE_ERROR;
goto ON_EXIT;
}
+
//
// The actual device address has been assigned by XHCI during initializing the device slot.
// So we just need establish the mapping relationship between the device address requested from UsbBus
@@ -955,7 +962,7 @@ XhcControlTransfer ( // can find out the actual device address by it.
//
Xhc->UsbDevContext[SlotId].BusDevAddr = (UINT8)Request->Value;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
goto ON_EXIT;
}
@@ -966,20 +973,20 @@ XhcControlTransfer ( // endpoint is bidirectional. XhcCreateUrb expects this
// combination of Ep addr and its direction.
//
- Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
- Status = XhcTransfer (
- Xhc,
- DeviceAddress,
- Endpoint,
- DeviceSpeed,
- MaximumPacketLength,
- XHC_CTRL_TRANSFER,
- Request,
- Data,
- DataLength,
- Timeout,
- TransferResult
- );
+ Endpoint = (UINT8)(0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
+ Status = XhcTransfer (
+ Xhc,
+ DeviceAddress,
+ Endpoint,
+ DeviceSpeed,
+ MaximumPacketLength,
+ XHC_CTRL_TRANSFER,
+ Request,
+ Data,
+ DataLength,
+ Timeout,
+ TransferResult
+ );
if (EFI_ERROR (Status)) {
goto ON_EXIT;
@@ -992,28 +999,30 @@ XhcControlTransfer ( //
if ((Request->Request == USB_REQ_GET_DESCRIPTOR) &&
((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)) ||
- ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE))))) {
+ ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE)))))
+ {
DescriptorType = (UINT8)(Request->Value >> 8);
if ((DescriptorType == USB_DESC_TYPE_DEVICE) && ((*DataLength == sizeof (EFI_USB_DEVICE_DESCRIPTOR)) || ((DeviceSpeed == EFI_USB_SPEED_FULL) && (*DataLength == 8)))) {
- ASSERT (Data != NULL);
+ ASSERT (Data != NULL);
+ //
+ // Store a copy of device scriptor as hub device need this info to configure endpoint.
+ //
+ CopyMem (&Xhc->UsbDevContext[SlotId].DevDesc, Data, *DataLength);
+ if (Xhc->UsbDevContext[SlotId].DevDesc.BcdUSB >= 0x0300) {
//
- // Store a copy of device scriptor as hub device need this info to configure endpoint.
+ // If it's a usb3.0 device, then its max packet size is a 2^n.
//
- CopyMem (&Xhc->UsbDevContext[SlotId].DevDesc, Data, *DataLength);
- if (Xhc->UsbDevContext[SlotId].DevDesc.BcdUSB >= 0x0300) {
- //
- // If it's a usb3.0 device, then its max packet size is a 2^n.
- //
- MaxPacket0 = 1 << Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
- } else {
- MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
- }
- Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool (Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));
- if (Xhc->HcCParams.Data.Csz == 0) {
- Status = XhcEvaluateContext (Xhc, SlotId, MaxPacket0);
- } else {
- Status = XhcEvaluateContext64 (Xhc, SlotId, MaxPacket0);
- }
+ MaxPacket0 = 1 << Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
+ } else {
+ MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
+ }
+
+ Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool (Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));
+ if (Xhc->HcCParams.Data.Csz == 0) {
+ Status = XhcEvaluateContext (Xhc, SlotId, MaxPacket0);
+ } else {
+ Status = XhcEvaluateContext64 (Xhc, SlotId, MaxPacket0);
+ }
} else if (DescriptorType == USB_DESC_TYPE_CONFIG) {
ASSERT (Data != NULL);
if (*DataLength == ((UINT16 *)Data)[1]) {
@@ -1022,7 +1031,7 @@ XhcControlTransfer ( //
Index = (UINT8)Request->Value;
ASSERT (Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations);
- Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool(*DataLength);
+ Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool (*DataLength);
CopyMem (Xhc->UsbDevContext[SlotId].ConfDesc[Index], Data, *DataLength);
//
// Default to use AlternateSetting 0 for all interfaces.
@@ -1030,7 +1039,8 @@ XhcControlTransfer ( Xhc->UsbDevContext[SlotId].ActiveAlternateSetting = AllocateZeroPool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]->NumInterfaces * sizeof (UINT8));
}
} else if (((DescriptorType == USB_DESC_TYPE_HUB) ||
- (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2)) {
+ (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2))
+ {
ASSERT (Data != NULL);
HubDesc = (EFI_USB_HUB_DESCRIPTOR *)Data;
ASSERT (HubDesc->NumPorts <= 15);
@@ -1055,7 +1065,8 @@ XhcControlTransfer ( }
}
} else if ((Request->Request == USB_REQ_SET_CONFIG) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)))
+ {
//
// Hook Set_Config request from UsbBus as we need configure device endpoint.
//
@@ -1066,17 +1077,19 @@ XhcControlTransfer ( } else {
Status = XhcSetConfigCmd64 (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
}
+
break;
}
}
} else if ((Request->Request == USB_REQ_SET_INTERFACE) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_INTERFACE))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_INTERFACE)))
+ {
//
// Hook Set_Interface request from UsbBus as we need configure interface setting.
// Request->Value indicates AlterlateSetting to set
// Request->Index indicates Interface to set
//
- if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] != (UINT8) Request->Value) {
+ if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8)Request->Index] != (UINT8)Request->Value) {
if (Xhc->HcCParams.Data.Csz == 0) {
Status = XhcSetInterface (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Xhc->UsbDevContext[SlotId].ActiveConfiguration - 1], Request);
} else {
@@ -1084,7 +1097,8 @@ XhcControlTransfer ( }
}
} else if ((Request->Request == USB_REQ_GET_STATUS) &&
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER))) {
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER)))
+ {
ASSERT (Data != NULL);
//
// Hook Get_Status request from UsbBus to keep track of the port status change.
@@ -1117,14 +1131,14 @@ XhcControlTransfer ( MapSize = sizeof (mUsbHubPortStateMap) / sizeof (USB_PORT_STATE_MAP);
for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbHubPortStateMap[Index].HwState)) {
- PortStatus.PortStatus = (UINT16) (PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);
+ PortStatus.PortStatus = (UINT16)(PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);
}
}
MapSize = sizeof (mUsbHubPortChangeMap) / sizeof (USB_PORT_STATE_MAP);
for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbHubPortChangeMap[Index].HwState)) {
- PortStatus.PortChangeStatus = (UINT16) (PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);
+ PortStatus.PortChangeStatus = (UINT16)(PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);
}
}
@@ -1133,11 +1147,11 @@ XhcControlTransfer ( for (Index = 0; Index < MapSize; Index++) {
if (XHC_BIT_IS_SET (State, mUsbHubClearPortChangeMap[Index].HwState)) {
ZeroMem (&ClearPortRequest, sizeof (EFI_USB_DEVICE_REQUEST));
- ClearPortRequest.RequestType = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);
- ClearPortRequest.Request = (UINT8) USB_REQ_CLEAR_FEATURE;
- ClearPortRequest.Value = mUsbHubClearPortChangeMap[Index].Selector;
- ClearPortRequest.Index = Request->Index;
- ClearPortRequest.Length = 0;
+ ClearPortRequest.RequestType = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);
+ ClearPortRequest.Request = (UINT8)USB_REQ_CLEAR_FEATURE;
+ ClearPortRequest.Value = mUsbHubClearPortChangeMap[Index].Selector;
+ ClearPortRequest.Index = Request->Index;
+ ClearPortRequest.Length = 0;
XhcControlTransfer (
This,
@@ -1157,7 +1171,7 @@ XhcControlTransfer ( XhcPollPortStatusChange (Xhc, Xhc->UsbDevContext[SlotId].RouteString, (UINT8)Request->Index, &PortStatus);
- *(UINT32 *)Data = *(UINT32*)&PortStatus;
+ *(UINT32 *)Data = *(UINT32 *)&PortStatus;
}
ON_EXIT:
@@ -1170,7 +1184,6 @@ ON_EXIT: return Status;
}
-
/**
Submits bulk transfer to a bulk endpoint of a USB device.
@@ -1218,16 +1231,17 @@ XhcBulkTransfer ( OUT UINT32 *TransferResult
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT8 SlotId;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT8 SlotId;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
//
// Validate the parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
- (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {
+ (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -1238,13 +1252,14 @@ XhcBulkTransfer ( if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)) ||
- ((EFI_USB_SPEED_SUPER == DeviceSpeed) && (MaximumPacketLength > 1024))) {
+ ((EFI_USB_SPEED_SUPER == DeviceSpeed) && (MaximumPacketLength > 1024)))
+ {
return EFI_INVALID_PARAMETER;
}
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
*TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
@@ -1284,6 +1299,7 @@ ON_EXIT: if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
+
gBS->RestoreTPL (OldTpl);
return Status;
@@ -1335,12 +1351,12 @@ XhcAsyncInterruptTransfer ( IN VOID *Context OPTIONAL
)
{
- USB_XHCI_INSTANCE *Xhc;
- URB *Urb;
- EFI_STATUS Status;
- UINT8 SlotId;
- UINT8 Index;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ URB *Urb;
+ EFI_STATUS Status;
+ UINT8 SlotId;
+ UINT8 Index;
+ EFI_TPL OldTpl;
//
// Validate parameters
@@ -1365,7 +1381,7 @@ XhcAsyncInterruptTransfer ( OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
//
// Delete Async interrupt transfer request.
@@ -1433,7 +1449,6 @@ ON_EXIT: return Status;
}
-
/**
Submits synchronous interrupt transfer to an interrupt endpoint
of a USB device.
@@ -1477,16 +1492,17 @@ XhcSyncInterruptTransfer ( OUT UINT32 *TransferResult
)
{
- USB_XHCI_INSTANCE *Xhc;
- UINT8 SlotId;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ UINT8 SlotId;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
//
// Validates parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
- (Data == NULL) || (TransferResult == NULL)) {
+ (Data == NULL) || (TransferResult == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -1496,13 +1512,14 @@ XhcSyncInterruptTransfer ( if (((DeviceSpeed == EFI_USB_SPEED_LOW) && (MaximumPacketLength != 8)) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
- ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 3072))) {
+ ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 3072)))
+ {
return EFI_INVALID_PARAMETER;
}
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = XHC_FROM_THIS (This);
+ Xhc = XHC_FROM_THIS (This);
*TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
@@ -1538,12 +1555,12 @@ ON_EXIT: if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcSyncInterruptTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
}
+
gBS->RestoreTPL (OldTpl);
return Status;
}
-
/**
Submits isochronous transfer to a target USB device.
@@ -1583,7 +1600,6 @@ XhcIsochronousTransfer ( return EFI_UNSUPPORTED;
}
-
/**
Submits Async isochronous transfer to a target USB device.
@@ -1639,8 +1655,8 @@ XhcAsyncIsochronousTransfer ( EFI_STATUS
EFIAPI
XhcDriverEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
return EfiLibInstallDriverBindingComponentName2 (
@@ -1653,7 +1669,6 @@ XhcDriverEntryPoint ( );
}
-
/**
Test to see if this driver supports ControllerHandle. Any
ControllerHandle that has Usb2HcProtocol installed will
@@ -1670,14 +1685,14 @@ XhcDriverEntryPoint ( EFI_STATUS
EFIAPI
XhcDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- USB_CLASSC UsbClassCReg;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ USB_CLASSC UsbClassCReg;
//
// Test whether there is PCI IO Protocol attached on the controller handle.
@@ -1685,7 +1700,7 @@ XhcDriverBindingSupported ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -1713,7 +1728,8 @@ XhcDriverBindingSupported ( //
if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) ||
(UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB) ||
- (UsbClassCReg.ProgInterface != PCI_IF_XHCI)) {
+ (UsbClassCReg.ProgInterface != PCI_IF_XHCI))
+ {
Status = EFI_UNSUPPORTED;
}
@@ -1739,18 +1755,18 @@ ON_EXIT: otherwise NULL.
**/
-USB_XHCI_INSTANCE*
+USB_XHCI_INSTANCE *
XhcCreateUsbHc (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
IN UINT64 OriginalPciAttributes
)
{
- USB_XHCI_INSTANCE *Xhc;
- EFI_STATUS Status;
- UINT32 PageSize;
- UINT16 ExtCapReg;
- UINT8 ReleaseNumber;
+ USB_XHCI_INSTANCE *Xhc;
+ EFI_STATUS Status;
+ UINT32 PageSize;
+ UINT16 ExtCapReg;
+ UINT8 ReleaseNumber;
Xhc = AllocateZeroPool (sizeof (USB_XHCI_INSTANCE));
@@ -1797,12 +1813,12 @@ XhcCreateUsbHc ( // This xHC supports a page size of 2^(n+12) if bit n is Set. For example,
// if bit 0 is Set, the xHC supports 4k byte page sizes.
//
- PageSize = XhcReadOpReg(Xhc, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;
- Xhc->PageSize = 1 << (HighBitSet32(PageSize) + 12);
+ PageSize = XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;
+ Xhc->PageSize = 1 << (HighBitSet32 (PageSize) + 12);
- ExtCapReg = (UINT16) (Xhc->HcCParams.Data.ExtCapReg);
- Xhc->ExtCapRegBase = ExtCapReg << 2;
- Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
+ ExtCapReg = (UINT16)(Xhc->HcCParams.Data.ExtCapReg);
+ Xhc->ExtCapRegBase = ExtCapReg << 2;
+ Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG);
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
@@ -1854,7 +1870,7 @@ XhcExitBootService ( USB_XHCI_INSTANCE *Xhc;
EFI_PCI_IO_PROTOCOL *PciIo;
- Xhc = (USB_XHCI_INSTANCE*) Context;
+ Xhc = (USB_XHCI_INSTANCE *)Context;
PciIo = Xhc->PciIo;
//
@@ -1874,11 +1890,11 @@ XhcExitBootService ( // Restore original PCI attributes
//
PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationSet,
- Xhc->OriginalPciAttributes,
- NULL
- );
+ PciIo,
+ EfiPciIoAttributeOperationSet,
+ Xhc->OriginalPciAttributes,
+ NULL
+ );
}
/**
@@ -1897,17 +1913,17 @@ XhcExitBootService ( EFI_STATUS
EFIAPI
XhcDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Supports;
- UINT64 OriginalPciAttributes;
- BOOLEAN PciAttributesSaved;
- USB_XHCI_INSTANCE *Xhc;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Supports;
+ UINT64 OriginalPciAttributes;
+ BOOLEAN PciAttributesSaved;
+ USB_XHCI_INSTANCE *Xhc;
EFI_DEVICE_PATH_PROTOCOL *HcDevicePath;
//
@@ -1916,7 +1932,7 @@ XhcDriverBindingStart ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciIoProtocolGuid,
- (VOID **) &PciIo,
+ (VOID **)&PciIo,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
@@ -1930,14 +1946,14 @@ XhcDriverBindingStart ( // Open Device Path Protocol for on USB host controller
//
HcDevicePath = NULL;
- Status = gBS->OpenProtocol (
- Controller,
- &gEfiDevicePathProtocolGuid,
- (VOID **) &HcDevicePath,
- This->DriverBindingHandle,
- Controller,
- EFI_OPEN_PROTOCOL_GET_PROTOCOL
- );
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ (VOID **)&HcDevicePath,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
+ );
PciAttributesSaved = FALSE;
//
@@ -1953,6 +1969,7 @@ XhcDriverBindingStart ( if (EFI_ERROR (Status)) {
goto CLOSE_PCIIO;
}
+
PciAttributesSaved = TRUE;
Status = PciIo->Attributes (
@@ -1963,12 +1980,12 @@ XhcDriverBindingStart ( );
if (!EFI_ERROR (Status)) {
Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
- Status = PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationEnable,
- Supports,
- NULL
- );
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ Supports,
+ NULL
+ );
}
if (EFI_ERROR (Status)) {
@@ -2000,9 +2017,13 @@ XhcDriverBindingStart ( if (!EFI_ERROR (Status)) {
Xhc->Support64BitDma = TRUE;
} else {
- DEBUG ((DEBUG_WARN,
+ DEBUG ((
+ DEBUG_WARN,
"%a: failed to enable 64-bit DMA on 64-bit capable controller @ %p (%r)\n",
- __FUNCTION__, Controller, Status));
+ __FUNCTION__,
+ Controller,
+ Status
+ ));
}
}
@@ -2025,7 +2046,7 @@ XhcDriverBindingStart ( //
// Start the Host Controller
//
- XhcRunHC(Xhc, XHC_GENERIC_TIMEOUT);
+ XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);
//
// Start the asynchronous interrupt monitor
@@ -2096,11 +2117,11 @@ CLOSE_PCIIO: // Restore original PCI attributes
//
PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationSet,
- OriginalPciAttributes,
- NULL
- );
+ PciIo,
+ EfiPciIoAttributeOperationSet,
+ OriginalPciAttributes,
+ NULL
+ );
}
gBS->CloseProtocol (
@@ -2113,7 +2134,6 @@ CLOSE_PCIIO: return Status;
}
-
/**
Stop this driver on ControllerHandle. Support stopping any child handles
created by this driver.
@@ -2130,10 +2150,10 @@ CLOSE_PCIIO: EFI_STATUS
EFIAPI
XhcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
)
{
EFI_STATUS Status;
@@ -2150,7 +2170,7 @@ XhcDriverBindingStop ( Status = gBS->OpenProtocol (
Controller,
&gEfiUsb2HcProtocolGuid,
- (VOID **) &Usb2Hc,
+ (VOID **)&Usb2Hc,
This->DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -2185,9 +2205,11 @@ XhcDriverBindingStop ( //
for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
- (Xhc->UsbDevContext[Index + 1].SlotId == 0)) {
+ (Xhc->UsbDevContext[Index + 1].SlotId == 0))
+ {
continue;
}
+
if (Xhc->HcCParams.Data.Csz == 0) {
XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
} else {
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h index 3285eb8..5054d79 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h @@ -29,8 +29,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <IndustryStandard/Pci.h>
-typedef struct _USB_XHCI_INSTANCE USB_XHCI_INSTANCE;
-typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
+typedef struct _USB_XHCI_INSTANCE USB_XHCI_INSTANCE;
+typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
#include "XhciReg.h"
#include "XhciSched.h"
@@ -40,62 +40,62 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT; //
// The unit is microsecond, setting it as 1us.
//
-#define XHC_1_MICROSECOND (1)
+#define XHC_1_MICROSECOND (1)
//
// The unit is microsecond, setting it as 1ms.
//
-#define XHC_1_MILLISECOND (1000)
+#define XHC_1_MILLISECOND (1000)
//
// XHC generic timeout experience values.
// The unit is millisecond, setting it as 10s.
//
-#define XHC_GENERIC_TIMEOUT (10 * 1000)
+#define XHC_GENERIC_TIMEOUT (10 * 1000)
//
// XHC reset timeout experience values.
// The unit is millisecond, setting it as 1s.
//
-#define XHC_RESET_TIMEOUT (1000)
+#define XHC_RESET_TIMEOUT (1000)
//
// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.
// The unit is microsecond, setting it as 10ms.
//
-#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
+#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
//
// XHC async transfer timer interval, set by experience.
// The unit is 100us, takes 1ms as interval.
//
-#define XHC_ASYNC_TIMER_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
+#define XHC_ASYNC_TIMER_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)
//
// XHC raises TPL to TPL_NOTIFY to serialize all its operations
// to protect shared data structures.
//
-#define XHC_TPL TPL_NOTIFY
+#define XHC_TPL TPL_NOTIFY
-#define CMD_RING_TRB_NUMBER 0x100
-#define TR_RING_TRB_NUMBER 0x100
-#define ERST_NUMBER 0x01
-#define EVENT_RING_TRB_NUMBER 0x200
+#define CMD_RING_TRB_NUMBER 0x100
+#define TR_RING_TRB_NUMBER 0x100
+#define ERST_NUMBER 0x01
+#define EVENT_RING_TRB_NUMBER 0x200
-#define CMD_INTER 0
-#define CTRL_INTER 1
-#define BULK_INTER 2
-#define INT_INTER 3
-#define INT_INTER_ASYNC 4
+#define CMD_INTER 0
+#define CTRL_INTER 1
+#define BULK_INTER 2
+#define INT_INTER 3
+#define INT_INTER_ASYNC 4
-#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
+#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
-#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
-#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
-#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
+#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
+#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
+#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define XHC_REG_BIT_IS_SET(Xhc, Offset, Bit) \
(XHC_BIT_IS_SET(XhcReadOpReg ((Xhc), (Offset)), (Bit)))
-#define XHCI_IS_DATAIN(EndpointAddr) XHC_BIT_IS_SET((EndpointAddr), 0x80)
+#define XHCI_IS_DATAIN(EndpointAddr) XHC_BIT_IS_SET((EndpointAddr), 0x80)
-#define XHCI_INSTANCE_SIG SIGNATURE_32 ('x', 'h', 'c', 'i')
-#define XHC_FROM_THIS(a) CR(a, USB_XHCI_INSTANCE, Usb2Hc, XHCI_INSTANCE_SIG)
+#define XHCI_INSTANCE_SIG SIGNATURE_32 ('x', 'h', 'c', 'i')
+#define XHC_FROM_THIS(a) CR(a, USB_XHCI_INSTANCE, Usb2Hc, XHCI_INSTANCE_SIG)
#define USB_DESC_TYPE_HUB 0x29
#define USB_DESC_TYPE_HUB_SUPER_SPEED 0x2a
@@ -113,19 +113,19 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT; //
#pragma pack(1)
typedef struct {
- UINT8 ProgInterface;
- UINT8 SubClassCode;
- UINT8 BaseCode;
+ UINT8 ProgInterface;
+ UINT8 SubClassCode;
+ UINT8 BaseCode;
} USB_CLASSC;
typedef struct {
- UINT8 Length;
- UINT8 DescType;
- UINT8 NumPorts;
- UINT16 HubCharacter;
- UINT8 PwrOn2PwrGood;
- UINT8 HubContrCurrent;
- UINT8 Filler[16];
+ UINT8 Length;
+ UINT8 DescType;
+ UINT8 NumPorts;
+ UINT16 HubCharacter;
+ UINT8 PwrOn2PwrGood;
+ UINT8 HubContrCurrent;
+ UINT8 Filler[16];
} EFI_USB_HUB_DESCRIPTOR;
#pragma pack()
@@ -133,23 +133,23 @@ struct _USB_DEV_CONTEXT { //
// Whether this entry in UsbDevContext array is used or not.
//
- BOOLEAN Enabled;
+ BOOLEAN Enabled;
//
// The slot id assigned to the new device through XHCI's Enable_Slot cmd.
//
- UINT8 SlotId;
+ UINT8 SlotId;
//
// The route string presented an attached usb device.
//
- USB_DEV_ROUTE RouteString;
+ USB_DEV_ROUTE RouteString;
//
// The route string of parent device if it exists. Otherwise it's zero.
//
- USB_DEV_ROUTE ParentRouteString;
+ USB_DEV_ROUTE ParentRouteString;
//
// The actual device address assigned by XHCI through Address_Device command.
//
- UINT8 XhciDevAddr;
+ UINT8 XhciDevAddr;
//
// The requested device address from UsbBus driver through Set_Address standard usb request.
// As XHCI spec replaces this request with Address_Device command, we have to record the
@@ -158,23 +158,23 @@ struct _USB_DEV_CONTEXT { // through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual
// device address and access the actual device.
//
- UINT8 BusDevAddr;
+ UINT8 BusDevAddr;
//
// The pointer to the input device context.
//
- VOID *InputContext;
+ VOID *InputContext;
//
// The pointer to the output device context.
//
- VOID *OutputContext;
+ VOID *OutputContext;
//
// The transfer queue for every endpoint.
//
- VOID *EndpointTransferRing[31];
+ VOID *EndpointTransferRing[31];
//
// The device descriptor which is stored to support XHCI's Evaluate_Context cmd.
//
- EFI_USB_DEVICE_DESCRIPTOR DevDesc;
+ EFI_USB_DEVICE_DESCRIPTOR DevDesc;
//
// As a usb device may include multiple configuration descriptors, we dynamically allocate an array
// to store them.
@@ -182,81 +182,80 @@ struct _USB_DEV_CONTEXT { // such as Interface descriptor, Endpoint descriptor, and so on.
// These information is used to support XHCI's Config_Endpoint cmd.
//
- EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
+ EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
//
// A device has an active Configuration.
//
- UINT8 ActiveConfiguration;
+ UINT8 ActiveConfiguration;
//
// Every interface has an active AlternateSetting.
//
- UINT8 *ActiveAlternateSetting;
+ UINT8 *ActiveAlternateSetting;
};
struct _USB_XHCI_INSTANCE {
- UINT32 Signature;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 OriginalPciAttributes;
- USBHC_MEM_POOL *MemPool;
+ UINT32 Signature;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 OriginalPciAttributes;
+ USBHC_MEM_POOL *MemPool;
- EFI_USB2_HC_PROTOCOL Usb2Hc;
+ EFI_USB2_HC_PROTOCOL Usb2Hc;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
//
// ExitBootServicesEvent is used to set OS semaphore and
// stop the XHC DMA operation after exit boot service.
//
- EFI_EVENT ExitBootServiceEvent;
- EFI_EVENT PollTimer;
- LIST_ENTRY AsyncIntTransfers;
-
- UINT8 CapLength; ///< Capability Register Length
- XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
- XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
- XHC_HCCPARAMS HcCParams; ///< Capability Parameters
- UINT32 DBOff; ///< Doorbell Offset
- UINT32 RTSOff; ///< Runtime Register Space Offset
- UINT16 MaxInterrupt;
- UINT32 PageSize;
- UINT64 *ScratchBuf;
- VOID *ScratchMap;
- UINT32 MaxScratchpadBufs;
- UINT64 *ScratchEntry;
- UINTN *ScratchEntryMap;
- UINT32 ExtCapRegBase;
- UINT32 UsbLegSupOffset;
- UINT32 DebugCapSupOffset;
- UINT64 *DCBAA;
- VOID *DCBAAMap;
- UINT32 MaxSlotsEn;
- URB *PendingUrb;
+ EFI_EVENT ExitBootServiceEvent;
+ EFI_EVENT PollTimer;
+ LIST_ENTRY AsyncIntTransfers;
+
+ UINT8 CapLength; ///< Capability Register Length
+ XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
+ XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
+ XHC_HCCPARAMS HcCParams; ///< Capability Parameters
+ UINT32 DBOff; ///< Doorbell Offset
+ UINT32 RTSOff; ///< Runtime Register Space Offset
+ UINT16 MaxInterrupt;
+ UINT32 PageSize;
+ UINT64 *ScratchBuf;
+ VOID *ScratchMap;
+ UINT32 MaxScratchpadBufs;
+ UINT64 *ScratchEntry;
+ UINTN *ScratchEntryMap;
+ UINT32 ExtCapRegBase;
+ UINT32 UsbLegSupOffset;
+ UINT32 DebugCapSupOffset;
+ UINT64 *DCBAA;
+ VOID *DCBAAMap;
+ UINT32 MaxSlotsEn;
+ URB *PendingUrb;
//
// Cmd Transfer Ring
//
- TRANSFER_RING CmdRing;
+ TRANSFER_RING CmdRing;
//
// EventRing
//
- EVENT_RING EventRing;
+ EVENT_RING EventRing;
//
// Misc
//
- EFI_UNICODE_STRING_TABLE *ControllerNameTable;
+ EFI_UNICODE_STRING_TABLE *ControllerNameTable;
//
// Store device contexts managed by XHCI instance
// The array supports up to 255 devices, entry 0 is reserved and should not be used.
//
- USB_DEV_CONTEXT UsbDevContext[256];
+ USB_DEV_CONTEXT UsbDevContext[256];
- BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
+ BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device
};
-
-extern EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding;
-extern EFI_COMPONENT_NAME_PROTOCOL gXhciComponentName;
-extern EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2;
+extern EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL gXhciComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2;
/**
Test to see if this driver supports ControllerHandle. Any
@@ -274,9 +273,9 @@ extern EFI_COMPONENT_NAME2_PROTOCOL gXhciComponentName2; EFI_STATUS
EFIAPI
XhcDriverBindingSupported (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -295,9 +294,9 @@ XhcDriverBindingSupported ( EFI_STATUS
EFIAPI
XhcDriverBindingStart (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
@@ -316,10 +315,10 @@ XhcDriverBindingStart ( EFI_STATUS
EFIAPI
XhcDriverBindingStop (
- IN EFI_DRIVER_BINDING_PROTOCOL *This,
- IN EFI_HANDLE Controller,
- IN UINTN NumberOfChildren,
- IN EFI_HANDLE *ChildHandleBuffer
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
);
/**
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c index 70102a7..80be331 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c @@ -21,18 +21,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
UINT8
XhcReadCapReg8 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT8 Data;
- EFI_STATUS Status;
+ UINT8 Data;
+ EFI_STATUS Status;
Status = Xhc->PciIo->Mem.Read (
Xhc->PciIo,
EfiPciIoWidthUint8,
XHC_BAR_INDEX,
- (UINT64) Offset,
+ (UINT64)Offset,
1,
&Data
);
@@ -57,18 +57,18 @@ XhcReadCapReg8 ( **/
UINT32
XhcReadCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
Status = Xhc->PciIo->Mem.Read (
Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
- (UINT64) Offset,
+ (UINT64)Offset,
1,
&Data
);
@@ -93,12 +93,12 @@ XhcReadCapReg ( **/
UINT32
XhcReadOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Xhc->CapLength != 0);
@@ -129,12 +129,12 @@ XhcReadOpReg ( **/
VOID
XhcWriteOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->CapLength != 0);
@@ -152,10 +152,6 @@ XhcWriteOpReg ( }
}
-
-
-
-
/**
Write the data to the XHCI door bell register.
@@ -166,12 +162,12 @@ XhcWriteOpReg ( **/
VOID
XhcWriteDoorBellReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->DBOff != 0);
@@ -200,12 +196,12 @@ XhcWriteDoorBellReg ( **/
UINT32
XhcReadRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Xhc->RTSOff != 0);
@@ -236,12 +232,12 @@ XhcReadRuntimeReg ( **/
VOID
XhcWriteRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->RTSOff != 0);
@@ -270,12 +266,12 @@ XhcWriteRuntimeReg ( **/
UINT32
XhcReadExtCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Xhc->ExtCapRegBase != 0);
@@ -306,12 +302,12 @@ XhcReadExtCapReg ( **/
VOID
XhcWriteExtCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->ExtCapRegBase != 0);
@@ -329,7 +325,6 @@ XhcWriteExtCapReg ( }
}
-
/**
Set one bit of the runtime register while keeping other bits.
@@ -340,12 +335,12 @@ XhcWriteExtCapReg ( **/
VOID
XhcSetRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadRuntimeReg (Xhc, Offset);
Data |= Bit;
@@ -362,12 +357,12 @@ XhcSetRuntimeRegBit ( **/
VOID
XhcClearRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadRuntimeReg (Xhc, Offset);
Data &= ~Bit;
@@ -384,19 +379,18 @@ XhcClearRuntimeRegBit ( **/
VOID
XhcSetOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadOpReg (Xhc, Offset);
Data |= Bit;
XhcWriteOpReg (Xhc, Offset, Data);
}
-
/**
Clear one bit of the operational register while keeping other bits.
@@ -407,12 +401,12 @@ XhcSetOpRegBit ( **/
VOID
XhcClearOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadOpReg (Xhc, Offset);
Data &= ~Bit;
@@ -436,15 +430,15 @@ XhcClearOpRegBit ( **/
EFI_STATUS
XhcWaitOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit,
- IN BOOLEAN WaitToSet,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit,
+ IN BOOLEAN WaitToSet,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
- EFI_EVENT TimeoutEvent;
+ EFI_STATUS Status;
+ EFI_EVENT TimeoutEvent;
TimeoutEvent = NULL;
@@ -460,15 +454,17 @@ XhcWaitOpRegBit ( &TimeoutEvent
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto DONE;
}
- Status = gBS->SetTimer (TimeoutEvent,
- TimerRelative,
- EFI_TIMER_PERIOD_MILLISECONDS(Timeout));
+ Status = gBS->SetTimer (
+ TimeoutEvent,
+ TimerRelative,
+ EFI_TIMER_PERIOD_MILLISECONDS (Timeout)
+ );
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto DONE;
}
@@ -479,7 +475,7 @@ XhcWaitOpRegBit ( }
gBS->Stall (XHC_1_MICROSECOND);
- } while (EFI_ERROR(gBS->CheckEvent (TimeoutEvent)));
+ } while (EFI_ERROR (gBS->CheckEvent (TimeoutEvent)));
Status = EFI_TIMEOUT;
@@ -499,10 +495,10 @@ DONE: **/
VOID
XhcSetBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- UINT32 Buffer;
+ UINT32 Buffer;
if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
return;
@@ -523,10 +519,10 @@ XhcSetBiosOwnership ( **/
VOID
XhcClearBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- UINT32 Buffer;
+ UINT32 Buffer;
if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
return;
@@ -550,13 +546,13 @@ XhcClearBiosOwnership ( **/
UINT32
XhcGetCapabilityAddr (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 CapId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 CapId
)
{
- UINT32 ExtCapOffset;
- UINT8 NextExtCapReg;
- UINT32 Data;
+ UINT32 ExtCapOffset;
+ UINT8 NextExtCapReg;
+ UINT32 Data;
ExtCapOffset = 0;
@@ -568,6 +564,7 @@ XhcGetCapabilityAddr ( if ((Data & 0xFF) == CapId) {
return ExtCapOffset;
}
+
//
// If not, then traverse all of the ext capability registers till finding out it.
//
@@ -589,13 +586,12 @@ XhcGetCapabilityAddr ( **/
BOOLEAN
XhcIsHalt (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);
}
-
/**
Whether system error occurred.
@@ -607,7 +603,7 @@ XhcIsHalt ( **/
BOOLEAN
XhcIsSysError (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);
@@ -627,11 +623,11 @@ XhcSetHsee ( IN USB_XHCI_INSTANCE *Xhc
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT16 XhciCmd;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT16 XhciCmd;
- PciIo = Xhc->PciIo;
+ PciIo = Xhc->PciIo;
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
@@ -658,11 +654,11 @@ XhcSetHsee ( **/
EFI_STATUS
XhcResetHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = EFI_SUCCESS;
@@ -679,7 +675,8 @@ XhcResetHC ( }
if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||
- ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {
+ ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0))
+ {
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
//
// Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.
@@ -701,7 +698,6 @@ XhcResetHC ( return Status;
}
-
/**
Halt the XHCI host controller.
@@ -714,18 +710,17 @@ XhcResetHC ( **/
EFI_STATUS
XhcHaltHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);
return Status;
}
-
/**
Set the XHCI host controller to run.
@@ -738,11 +733,11 @@ XhcHaltHC ( **/
EFI_STATUS
XhcRunHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h index cc5c1bf..4950eed 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h @@ -10,124 +10,124 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_XHCI_REG_H_
#define _EFI_XHCI_REG_H_
-#define PCI_IF_XHCI 0x30
+#define PCI_IF_XHCI 0x30
//
// PCI Configuration Registers
//
-#define XHC_BAR_INDEX 0x00
+#define XHC_BAR_INDEX 0x00
-#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
-#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
+#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
+#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
-#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset
+#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset
-#define USB_HUB_CLASS_CODE 0x09
-#define USB_HUB_SUBCLASS_CODE 0x00
+#define USB_HUB_CLASS_CODE 0x09
+#define USB_HUB_SUBCLASS_CODE 0x00
-#define XHC_CAP_USB_LEGACY 0x01
-#define XHC_CAP_USB_DEBUG 0x0A
+#define XHC_CAP_USB_LEGACY 0x01
+#define XHC_CAP_USB_DEBUG 0x0A
-//============================================//
+// ============================================//
// XHCI register offset //
-//============================================//
+// ============================================//
//
// Capability registers offset
//
-#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
-#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
-#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
-#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
-#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
-#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
-#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
-#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
+#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
+#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
+#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
+#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
+#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
+#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
+#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
+#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
//
// Operational registers offset
//
-#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
-#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
-#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
-#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
-#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
-#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
-#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
-#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
+#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
+#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
+#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
+#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
+#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
+#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
+#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
+#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
//
// Runtime registers offset
//
-#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
-#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
-#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
-#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
-#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
-#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
+#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
+#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
+#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
+#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
+#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
+#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
//
// Debug registers offset
//
-#define XHC_DC_DCCTRL 0x20
+#define XHC_DC_DCCTRL 0x20
-#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
-#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
+#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
+#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
#pragma pack (1)
typedef struct {
- UINT8 MaxSlots; // Number of Device Slots
- UINT16 MaxIntrs:11; // Number of Interrupters
- UINT16 Rsvd:5;
- UINT8 MaxPorts; // Number of Ports
+ UINT8 MaxSlots; // Number of Device Slots
+ UINT16 MaxIntrs : 11; // Number of Interrupters
+ UINT16 Rsvd : 5;
+ UINT8 MaxPorts; // Number of Ports
} HCSPARAMS1;
//
// Structural Parameters 1 Register Bitmap Definition
//
typedef union {
- UINT32 Dword;
- HCSPARAMS1 Data;
+ UINT32 Dword;
+ HCSPARAMS1 Data;
} XHC_HCSPARAMS1;
typedef struct {
- UINT32 Ist:4; // Isochronous Scheduling Threshold
- UINT32 Erst:4; // Event Ring Segment Table Max
- UINT32 Rsvd:13;
- UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi
- UINT32 Spr:1; // Scratchpad Restore
- UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo
+ UINT32 Ist : 4; // Isochronous Scheduling Threshold
+ UINT32 Erst : 4; // Event Ring Segment Table Max
+ UINT32 Rsvd : 13;
+ UINT32 ScratchBufHi : 5; // Max Scratchpad Buffers Hi
+ UINT32 Spr : 1; // Scratchpad Restore
+ UINT32 ScratchBufLo : 5; // Max Scratchpad Buffers Lo
} HCSPARAMS2;
//
// Structural Parameters 2 Register Bitmap Definition
//
typedef union {
- UINT32 Dword;
- HCSPARAMS2 Data;
+ UINT32 Dword;
+ HCSPARAMS2 Data;
} XHC_HCSPARAMS2;
typedef struct {
- UINT16 Ac64:1; // 64-bit Addressing Capability
- UINT16 Bnc:1; // BW Negotiation Capability
- UINT16 Csz:1; // Context Size
- UINT16 Ppc:1; // Port Power Control
- UINT16 Pind:1; // Port Indicators
- UINT16 Lhrc:1; // Light HC Reset Capability
- UINT16 Ltc:1; // Latency Tolerance Messaging Capability
- UINT16 Nss:1; // No Secondary SID Support
- UINT16 Pae:1; // Parse All Event Data
- UINT16 Rsvd:3;
- UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size
- UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
+ UINT16 Ac64 : 1; // 64-bit Addressing Capability
+ UINT16 Bnc : 1; // BW Negotiation Capability
+ UINT16 Csz : 1; // Context Size
+ UINT16 Ppc : 1; // Port Power Control
+ UINT16 Pind : 1; // Port Indicators
+ UINT16 Lhrc : 1; // Light HC Reset Capability
+ UINT16 Ltc : 1; // Latency Tolerance Messaging Capability
+ UINT16 Nss : 1; // No Secondary SID Support
+ UINT16 Pae : 1; // Parse All Event Data
+ UINT16 Rsvd : 3;
+ UINT16 MaxPsaSize : 4; // Maximum Primary Stream Array Size
+ UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
} HCCPARAMS;
//
// Capability Parameters Register Bitmap Definition
//
typedef union {
- UINT32 Dword;
- HCCPARAMS Data;
+ UINT32 Dword;
+ HCCPARAMS Data;
} XHC_HCCPARAMS;
#pragma pack ()
@@ -135,62 +135,62 @@ typedef union { //
// Register Bit Definition
//
-#define XHC_USBCMD_RUN BIT0 // Run/Stop
-#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
-#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
-#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
-
-#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
-#define XHC_USBSTS_HSE BIT2 // Host System Error
-#define XHC_USBSTS_EINT BIT3 // Event Interrupt
-#define XHC_USBSTS_PCD BIT4 // Port Change Detect
-#define XHC_USBSTS_SSS BIT8 // Save State Status
-#define XHC_USBSTS_RSS BIT9 // Restore State Status
-#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
-#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
-#define XHC_USBSTS_HCE BIT12 // Host Controller Error
-
-#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
-
-#define XHC_CRCR_RCS BIT0 // Ring Cycle State
-#define XHC_CRCR_CS BIT1 // Command Stop
-#define XHC_CRCR_CA BIT2 // Command Abort
-#define XHC_CRCR_CRR BIT3 // Command Ring Running
-
-#define XHC_CONFIG_MASK 0xFF // Command Ring Running
-
-#define XHC_PORTSC_CCS BIT0 // Current Connect Status
-#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
-#define XHC_PORTSC_OCA BIT3 // Over-current Active
-#define XHC_PORTSC_RESET BIT4 // Port Reset
-#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
-#define XHC_PORTSC_PP BIT9 // Port Power
-#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
-#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
-#define XHC_PORTSC_CSC BIT17 // Connect Status Change
-#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
-#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
-#define XHC_PORTSC_OCC BIT20 // Over-Current Change
-#define XHC_PORTSC_PRC BIT21 // Port Reset Change
-#define XHC_PORTSC_PLC BIT22 // Port Link State Change
-#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
-#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
-
-#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
-#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
-#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
-#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
-#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
-#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
-#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
-#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
-#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
-#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
-#define XHC_IMAN_IP BIT0 // Interrupt Pending
-#define XHC_IMAN_IE BIT1 // Interrupt Enable
-
-#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
-#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
+#define XHC_USBCMD_RUN BIT0 // Run/Stop
+#define XHC_USBCMD_RESET BIT1 // Host Controller Reset
+#define XHC_USBCMD_INTE BIT2 // Interrupter Enable
+#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
+
+#define XHC_USBSTS_HALT BIT0 // Host Controller Halted
+#define XHC_USBSTS_HSE BIT2 // Host System Error
+#define XHC_USBSTS_EINT BIT3 // Event Interrupt
+#define XHC_USBSTS_PCD BIT4 // Port Change Detect
+#define XHC_USBSTS_SSS BIT8 // Save State Status
+#define XHC_USBSTS_RSS BIT9 // Restore State Status
+#define XHC_USBSTS_SRE BIT10 // Save/Restore Error
+#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
+#define XHC_USBSTS_HCE BIT12 // Host Controller Error
+
+#define XHC_PAGESIZE_MASK 0xFFFF // Page Size
+
+#define XHC_CRCR_RCS BIT0 // Ring Cycle State
+#define XHC_CRCR_CS BIT1 // Command Stop
+#define XHC_CRCR_CA BIT2 // Command Abort
+#define XHC_CRCR_CRR BIT3 // Command Ring Running
+
+#define XHC_CONFIG_MASK 0xFF // Command Ring Running
+
+#define XHC_PORTSC_CCS BIT0 // Current Connect Status
+#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
+#define XHC_PORTSC_OCA BIT3 // Over-current Active
+#define XHC_PORTSC_RESET BIT4 // Port Reset
+#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
+#define XHC_PORTSC_PP BIT9 // Port Power
+#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed
+#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
+#define XHC_PORTSC_CSC BIT17 // Connect Status Change
+#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
+#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
+#define XHC_PORTSC_OCC BIT20 // Over-Current Change
+#define XHC_PORTSC_PRC BIT21 // Port Reset Change
+#define XHC_PORTSC_PLC BIT22 // Port Link State Change
+#define XHC_PORTSC_CEC BIT23 // Port Config Error Change
+#define XHC_PORTSC_CAS BIT24 // Cold Attach Status
+
+#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
+#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
+#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
+#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
+#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
+#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
+#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
+#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
+#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
+#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
+#define XHC_IMAN_IP BIT0 // Interrupt Pending
+#define XHC_IMAN_IE BIT1 // Interrupt Enable
+
+#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
+#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
//
// Hub Class Feature Selector for Clear Port Feature Request
@@ -198,8 +198,8 @@ typedef union { // For more details, Please refer to USB 3.0 Spec Table 10-7.
//
typedef enum {
- Usb3PortBHPortReset = 28,
- Usb3PortBHPortResetChange = 29
+ Usb3PortBHPortReset = 28,
+ Usb3PortBHPortResetChange = 29
} XHC_PORT_FEATURE;
//
@@ -207,16 +207,16 @@ typedef enum { // UEFI's port states.
//
typedef struct {
- UINT32 HwState;
- UINT16 UefiState;
+ UINT32 HwState;
+ UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
// Structure to map the hardware port states to feature selector for clear port feature request.
//
typedef struct {
- UINT32 HwState;
- UINT16 Selector;
+ UINT32 HwState;
+ UINT16 Selector;
} USB_CLEAR_PORT_MAP;
/**
@@ -231,8 +231,8 @@ typedef struct { **/
UINT8
XhcReadCapReg8 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -247,8 +247,8 @@ XhcReadCapReg8 ( **/
UINT32
XhcReadCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -263,8 +263,8 @@ XhcReadCapReg ( **/
UINT32
XhcReadOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -277,12 +277,11 @@ XhcReadOpReg ( **/
VOID
XhcWriteOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
-
/**
Read XHCI runtime register.
@@ -294,8 +293,8 @@ XhcWriteOpReg ( **/
UINT32
XhcReadRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -308,12 +307,11 @@ XhcReadRuntimeReg ( **/
VOID
XhcWriteRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
-
/**
Write the data to the XHCI door bell register.
@@ -324,9 +322,9 @@ XhcWriteRuntimeReg ( **/
VOID
XhcWriteDoorBellReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
/**
@@ -339,9 +337,9 @@ XhcWriteDoorBellReg ( **/
VOID
XhcSetOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -354,9 +352,9 @@ XhcSetOpRegBit ( **/
VOID
XhcClearOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -375,11 +373,11 @@ XhcClearOpRegBit ( **/
EFI_STATUS
XhcWaitOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit,
- IN BOOLEAN WaitToSet,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit,
+ IN BOOLEAN WaitToSet,
+ IN UINT32 Timeout
);
/**
@@ -393,8 +391,8 @@ XhcWaitOpRegBit ( **/
UINT32
XhcReadRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -407,9 +405,9 @@ XhcReadRuntimeReg ( **/
VOID
XhcWriteRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
);
/**
@@ -422,9 +420,9 @@ XhcWriteRuntimeReg ( **/
VOID
XhcSetRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -437,9 +435,9 @@ XhcSetRuntimeRegBit ( **/
VOID
XhcClearRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
);
/**
@@ -453,8 +451,8 @@ XhcClearRuntimeRegBit ( **/
UINT32
XhcReadExtCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
);
/**
@@ -468,7 +466,7 @@ XhcReadExtCapReg ( **/
BOOLEAN
XhcIsHalt (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -482,7 +480,7 @@ XhcIsHalt ( **/
BOOLEAN
XhcIsSysError (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -497,8 +495,8 @@ XhcIsSysError ( **/
EFI_STATUS
XhcResetHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
);
/**
@@ -513,8 +511,8 @@ XhcResetHC ( **/
EFI_STATUS
XhcHaltHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
);
/**
@@ -529,8 +527,8 @@ XhcHaltHC ( **/
EFI_STATUS
XhcRunHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
);
/**
@@ -544,8 +542,8 @@ XhcRunHC ( **/
UINT32
XhcGetCapabilityAddr (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 CapId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 CapId
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c index 92f63c2..c2906e0 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -19,25 +19,25 @@ SPDX-License-Identifier: BSD-2-Clause-Patent @return Created URB or NULL.
**/
-URB*
+URB *
XhcCreateCmdTrb (
IN USB_XHCI_INSTANCE *Xhc,
IN TRB_TEMPLATE *CmdTrb
)
{
- URB *Urb;
+ URB *Urb;
Urb = AllocateZeroPool (sizeof (URB));
if (Urb == NULL) {
return NULL;
}
- Urb->Signature = XHC_URB_SIG;
+ Urb->Signature = XHC_URB_SIG;
- Urb->Ring = &Xhc->CmdRing;
+ Urb->Ring = &Xhc->CmdRing;
XhcSyncTrsRing (Xhc, Urb->Ring);
- Urb->TrbNum = 1;
- Urb->TrbStart = Urb->Ring->RingEnqueue;
+ Urb->TrbNum = 1;
+ Urb->TrbStart = Urb->Ring->RingEnqueue;
CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));
Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;
Urb->TrbEnd = Urb->TrbStart;
@@ -63,14 +63,14 @@ XhcCreateCmdTrb ( EFI_STATUS
EFIAPI
XhcCmdTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN TRB_TEMPLATE *CmdTrb,
- IN UINTN Timeout,
- OUT TRB_TEMPLATE **EvtTrb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN TRB_TEMPLATE *CmdTrb,
+ IN UINTN Timeout,
+ OUT TRB_TEMPLATE **EvtTrb
)
{
- EFI_STATUS Status;
- URB *Urb;
+ EFI_STATUS Status;
+ URB *Urb;
//
// Validate the parameters
@@ -128,24 +128,24 @@ ON_EXIT: @return Created URB or NULL
**/
-URB*
+URB *
XhcCreateUrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
)
{
- USB_ENDPOINT *Ep;
- EFI_STATUS Status;
- URB *Urb;
+ USB_ENDPOINT *Ep;
+ EFI_STATUS Status;
+ URB *Urb;
Urb = AllocateZeroPool (sizeof (URB));
if (Urb == NULL) {
@@ -189,8 +189,8 @@ XhcCreateUrb ( **/
VOID
XhcFreeUrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
if ((Xhc == NULL) || (Urb == NULL)) {
@@ -215,23 +215,23 @@ XhcFreeUrb ( **/
EFI_STATUS
XhcCreateTransferTrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- VOID *OutputContext;
- TRANSFER_RING *EPRing;
- UINT8 EPType;
- UINT8 SlotId;
- UINT8 Dci;
- TRB *TrbStart;
- UINTN TotalLen;
- UINTN Len;
- UINTN TrbNum;
- EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *Map;
- EFI_STATUS Status;
+ VOID *OutputContext;
+ TRANSFER_RING *EPRing;
+ UINT8 EPType;
+ UINT8 SlotId;
+ UINT8 Dci;
+ TRB *TrbStart;
+ UINTN TotalLen;
+ UINTN Len;
+ UINTN TrbNum;
+ EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *Map;
+ EFI_STATUS Status;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
@@ -244,37 +244,37 @@ XhcCreateTransferTrb ( Urb->Completed = 0;
Urb->Result = EFI_USB_NOERROR;
- Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
+ Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
- EPRing = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
- Urb->Ring = EPRing;
+ EPRing = (TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
+ Urb->Ring = EPRing;
OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
if (Xhc->HcCParams.Data.Csz == 0) {
- EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
+ EPType = (UINT8)((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
} else {
- EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
+ EPType = (UINT8)((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
}
//
// No need to remap.
//
if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {
- if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
+ if (((UINT8)(Urb->Ep.Direction)) == EfiUsbDataIn) {
MapOp = EfiPciIoOperationBusMasterWrite;
} else {
MapOp = EfiPciIoOperationBusMasterRead;
}
- Len = Urb->DataLen;
- Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
+ Len = Urb->DataLen;
+ Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
return EFI_OUT_OF_RESOURCES;
}
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
- Urb->DataMap = Map;
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
+ Urb->DataMap = Map;
}
//
@@ -287,7 +287,7 @@ XhcCreateTransferTrb ( //
// For control transfer, create SETUP_STAGE_TRB first.
//
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;
TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;
TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;
@@ -310,6 +310,7 @@ XhcCreateTransferTrb ( } else {
TrbStart->TrbCtrSetup.TRT = 0;
}
+
//
// Update the cycle bit
//
@@ -321,10 +322,10 @@ XhcCreateTransferTrb ( //
if (Urb->DataLen > 0) {
XhcSyncTrsRing (Xhc, EPRing);
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->DataPhy);
- TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->DataPhy);
- TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT (Urb->DataPhy);
+ TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT (Urb->DataPhy);
+ TrbStart->TrbCtrData.Length = (UINT32)Urb->DataLen;
TrbStart->TrbCtrData.TDSize = 0;
TrbStart->TrbCtrData.IntTarget = 0;
TrbStart->TrbCtrData.ISP = 1;
@@ -339,18 +340,20 @@ XhcCreateTransferTrb ( } else {
TrbStart->TrbCtrData.DIR = 0;
}
+
//
// Update the cycle bit
//
TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;
Urb->TrbNum++;
}
+
//
// For control transfer, create STATUS_STAGE_TRB.
// Get the pointer to next TRB for status stage use
//
XhcSyncTrsRing (Xhc, EPRing);
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrStatus.IntTarget = 0;
TrbStart->TrbCtrStatus.IOC = 1;
TrbStart->TrbCtrStatus.CH = 0;
@@ -362,6 +365,7 @@ XhcCreateTransferTrb ( } else {
TrbStart->TrbCtrStatus.DIR = 0;
}
+
//
// Update the cycle bit
//
@@ -387,10 +391,11 @@ XhcCreateTransferTrb ( } else {
Len = 0x10000;
}
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.Length = (UINT32) Len;
+
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.Length = (UINT32)Len;
TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1;
@@ -422,10 +427,11 @@ XhcCreateTransferTrb ( } else {
Len = 0x10000;
}
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.Length = (UINT32) Len;
+
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.Length = (UINT32)Len;
TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1;
@@ -446,7 +452,7 @@ XhcCreateTransferTrb ( break;
default:
- DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n",EPType));
+ DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n", EPType));
ASSERT (FALSE);
break;
}
@@ -454,7 +460,6 @@ XhcCreateTransferTrb ( return EFI_SUCCESS;
}
-
/**
Initialize the XHCI host controller for schedule.
@@ -463,7 +468,7 @@ XhcCreateTransferTrb ( **/
VOID
XhcInitSched (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
VOID *Dcbaa;
@@ -500,8 +505,8 @@ XhcInitSched ( // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
// Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
//
- Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);
- Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries);
+ Entries = (Xhc->MaxSlotsEn + 1) * sizeof (UINT64);
+ Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries);
ASSERT (Dcbaa != NULL);
ZeroMem (Dcbaa, Entries);
@@ -529,14 +534,14 @@ XhcInitSched ( Xhc->ScratchEntry = ScratchEntry;
ScratchPhy = 0;
- Status = UsbHcAllocateAlignedPages (
- Xhc->PciIo,
- EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
- Xhc->PageSize,
- (VOID **) &ScratchBuf,
- &ScratchPhy,
- &Xhc->ScratchMap
- );
+ Status = UsbHcAllocateAlignedPages (
+ Xhc->PciIo,
+ EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
+ Xhc->PageSize,
+ (VOID **)&ScratchBuf,
+ &ScratchPhy,
+ &Xhc->ScratchMap
+ );
ASSERT_EFI_ERROR (Status);
ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));
@@ -547,14 +552,14 @@ XhcInitSched ( //
for (Index = 0; Index < MaxScratchpadBufs; Index++) {
ScratchEntryPhy = 0;
- Status = UsbHcAllocateAlignedPages (
- Xhc->PciIo,
- EFI_SIZE_TO_PAGES (Xhc->PageSize),
- Xhc->PageSize,
- (VOID **) &ScratchEntry[Index],
- &ScratchEntryPhy,
- (VOID **) &ScratchEntryMap[Index]
- );
+ Status = UsbHcAllocateAlignedPages (
+ Xhc->PciIo,
+ EFI_SIZE_TO_PAGES (Xhc->PageSize),
+ Xhc->PageSize,
+ (VOID **)&ScratchEntry[Index],
+ &ScratchEntryPhy,
+ (VOID **)&ScratchEntryMap[Index]
+ );
ASSERT_EFI_ERROR (Status);
ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);
//
@@ -562,11 +567,12 @@ XhcInitSched ( //
*ScratchBuf++ = ScratchEntryPhy;
}
+
//
// The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
// Device Context Base Address Array points to the Scratchpad Buffer Array.
//
- *(UINT64 *)Dcbaa = (UINT64)(UINTN) ScratchPhy;
+ *(UINT64 *)Dcbaa = (UINT64)(UINTN)ScratchPhy;
}
//
@@ -579,7 +585,7 @@ XhcInitSched ( // So divide it to two 32-bytes width register access.
//
DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries);
- XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(DcbaaPhy));
+ XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy));
XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
DEBUG ((DEBUG_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
@@ -596,15 +602,15 @@ XhcInitSched ( // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
// So we set RCS as inverted PCS init value to let Command Ring empty
//
- CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
- CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN) CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
+ CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
+ CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
ASSERT ((CmdRingPhy & 0x3F) == 0);
CmdRingPhy |= XHC_CRCR_RCS;
//
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
//
- XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRingPhy));
+ XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT (CmdRingPhy));
XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));
//
@@ -621,9 +627,13 @@ XhcInitSched ( // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
//
CreateEventRing (Xhc, &Xhc->EventRing);
- DEBUG ((DEBUG_INFO, "XhcInitSched: Created CMD ring [%p~%p) EVENT ring [%p~%p)\n",
- Xhc->CmdRing.RingSeg0, (UINTN)Xhc->CmdRing.RingSeg0 + sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,
- Xhc->EventRing.EventRingSeg0, (UINTN)Xhc->EventRing.EventRingSeg0 + sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER
+ DEBUG ((
+ DEBUG_INFO,
+ "XhcInitSched: Created CMD ring [%p~%p) EVENT ring [%p~%p)\n",
+ Xhc->CmdRing.RingSeg0,
+ (UINTN)Xhc->CmdRing.RingSeg0 + sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,
+ Xhc->EventRing.EventRingSeg0,
+ (UINTN)Xhc->EventRing.EventRingSeg0 + sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER
));
}
@@ -644,19 +654,20 @@ XhcInitSched ( EFI_STATUS
EFIAPI
XhcRecoverHaltedEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- UINT8 Dci;
- UINT8 SlotId;
+ EFI_STATUS Status;
+ UINT8 Dci;
+ UINT8 SlotId;
Status = EFI_SUCCESS;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
+
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
@@ -665,8 +676,8 @@ XhcRecoverHaltedEndpoint ( //
// 1) Send Reset endpoint command to transit from halt to stop state
//
- Status = XhcResetEndpoint(Xhc, SlotId, Dci);
- if (EFI_ERROR(Status)) {
+ Status = XhcResetEndpoint (Xhc, SlotId, Dci);
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -674,8 +685,8 @@ XhcRecoverHaltedEndpoint ( //
// 2)Set dequeue pointer
//
- Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
- if (EFI_ERROR(Status)) {
+ Status = XhcSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
}
@@ -706,19 +717,20 @@ Done: EFI_STATUS
EFIAPI
XhcDequeueTrbFromEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- UINT8 Dci;
- UINT8 SlotId;
+ EFI_STATUS Status;
+ UINT8 Dci;
+ UINT8 SlotId;
Status = EFI_SUCCESS;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
+
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
@@ -727,8 +739,8 @@ XhcDequeueTrbFromEndpoint ( //
// 1) Send Stop endpoint command to stop xHC from executing of the TDs on the endpoint
//
- Status = XhcStopEndpoint(Xhc, SlotId, Dci, Urb);
- if (EFI_ERROR(Status)) {
+ Status = XhcStopEndpoint (Xhc, SlotId, Dci, Urb);
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -736,7 +748,7 @@ XhcDequeueTrbFromEndpoint ( //
// 2)Set dequeue pointer
//
- if (Urb->Finished && Urb->Result == EFI_USB_NOERROR) {
+ if (Urb->Finished && (Urb->Result == EFI_USB_NOERROR)) {
//
// Return Already Started to indicate the pending URB is finished.
// This fixes BULK data loss when transfer is detected as timeout
@@ -745,7 +757,7 @@ XhcDequeueTrbFromEndpoint ( Status = EFI_ALREADY_STARTED;
DEBUG ((DEBUG_INFO, "XhcDequeueTrbFromEndpoint: Pending URB is finished: Length Actual/Expect = %d/%d!\n", Urb->Completed, Urb->DataLen));
} else {
- Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
+ Status = XhcSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
@@ -770,8 +782,8 @@ Done: **/
VOID
CreateEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- OUT EVENT_RING *EventRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ OUT EVENT_RING *EventRing
)
{
VOID *Buf;
@@ -783,15 +795,15 @@ CreateEventRing ( ASSERT (EventRing != NULL);
Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;
- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, Size);
EventRing->EventRingSeg0 = Buf;
EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
- EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
- EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
+ EventRing->EventRingDequeue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;
+ EventRing->EventRingEnqueue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;
DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
@@ -802,12 +814,12 @@ CreateEventRing ( EventRing->EventRingCCS = 1;
Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;
- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, Size);
- ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
+ ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *)Buf;
EventRing->ERSTBase = ERSTBase;
ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);
ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);
@@ -832,12 +844,12 @@ CreateEventRing ( XhcWriteRuntimeReg (
Xhc,
XHC_ERDP_OFFSET,
- XHC_LOW_32BIT((UINT64)(UINTN)DequeuePhy)
+ XHC_LOW_32BIT ((UINT64)(UINTN)DequeuePhy)
);
XhcWriteRuntimeReg (
Xhc,
XHC_ERDP_OFFSET + 4,
- XHC_HIGH_32BIT((UINT64)(UINTN)DequeuePhy)
+ XHC_HIGH_32BIT ((UINT64)(UINTN)DequeuePhy)
);
//
// Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
@@ -848,12 +860,12 @@ CreateEventRing ( XhcWriteRuntimeReg (
Xhc,
XHC_ERSTBA_OFFSET,
- XHC_LOW_32BIT((UINT64)(UINTN)ERSTPhy)
+ XHC_LOW_32BIT ((UINT64)(UINTN)ERSTPhy)
);
XhcWriteRuntimeReg (
Xhc,
XHC_ERSTBA_OFFSET + 4,
- XHC_HIGH_32BIT((UINT64)(UINTN)ERSTPhy)
+ XHC_HIGH_32BIT ((UINT64)(UINTN)ERSTPhy)
);
//
// Need set IMAN IE bit to enble the ring interrupt
@@ -871,9 +883,9 @@ CreateEventRing ( **/
VOID
CreateTransferRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINTN TrbNum,
- OUT TRANSFER_RING *TransferRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINTN TrbNum,
+ OUT TRANSFER_RING *TransferRing
)
{
VOID *Buf;
@@ -882,28 +894,28 @@ CreateTransferRing ( Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
- TransferRing->RingSeg0 = Buf;
- TransferRing->TrbNumber = TrbNum;
- TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
- TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
- TransferRing->RingPCS = 1;
+ TransferRing->RingSeg0 = Buf;
+ TransferRing->TrbNumber = TrbNum;
+ TransferRing->RingEnqueue = (TRB_TEMPLATE *)TransferRing->RingSeg0;
+ TransferRing->RingDequeue = (TRB_TEMPLATE *)TransferRing->RingSeg0;
+ TransferRing->RingPCS = 1;
//
// 4.9.2 Transfer Ring Management
// To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
// point to the first TRB in the ring.
//
- EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
+ EndTrb = (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
EndTrb->Type = TRB_TYPE_LINK;
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);
EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);
//
// Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
//
- EndTrb->TC = 1;
+ EndTrb->TC = 1;
//
// Set Cycle bit as other TRB PCS init value
//
@@ -920,11 +932,11 @@ CreateTransferRing ( EFI_STATUS
EFIAPI
XhcFreeEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN EVENT_RING *EventRing
-)
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN EVENT_RING *EventRing
+ )
{
- if(EventRing->EventRingSeg0 == NULL) {
+ if (EventRing->EventRingSeg0 == NULL) {
return EFI_SUCCESS;
}
@@ -948,11 +960,11 @@ XhcFreeEventRing ( **/
VOID
XhcFreeSched (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- UINT32 Index;
- UINT64 *ScratchEntry;
+ UINT32 Index;
+ UINT64 *ScratchEntry;
if (Xhc->ScratchBuf != NULL) {
ScratchEntry = Xhc->ScratchEntry;
@@ -960,8 +972,9 @@ XhcFreeSched ( //
// Free Scratchpad Buffers
//
- UsbHcFreeAlignedPages (Xhc->PciIo, (VOID*)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);
+ UsbHcFreeAlignedPages (Xhc->PciIo, (VOID *)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *)Xhc->ScratchEntryMap[Index]);
}
+
//
// Free Scratchpad Buffer Array
//
@@ -975,10 +988,10 @@ XhcFreeSched ( Xhc->CmdRing.RingSeg0 = NULL;
}
- XhcFreeEventRing (Xhc,&Xhc->EventRing);
+ XhcFreeEventRing (Xhc, &Xhc->EventRing);
if (Xhc->DCBAA != NULL) {
- UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof(UINT64));
+ UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof (UINT64));
Xhc->DCBAA = NULL;
}
@@ -1004,30 +1017,31 @@ XhcFreeSched ( **/
BOOLEAN
IsTransferRingTrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN TRB_TEMPLATE *Trb,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN TRB_TEMPLATE *Trb,
+ IN URB *Urb
)
{
- LINK_TRB *LinkTrb;
- TRB_TEMPLATE *CheckedTrb;
- UINTN Index;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ LINK_TRB *LinkTrb;
+ TRB_TEMPLATE *CheckedTrb;
+ UINTN Index;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
CheckedTrb = Urb->TrbStart;
for (Index = 0; Index < Urb->TrbNum; Index++) {
if (Trb == CheckedTrb) {
return TRUE;
}
+
CheckedTrb++;
//
// If the checked TRB is the link TRB at the end of the transfer ring,
// recircle it to the head of the ring.
//
if (CheckedTrb->Type == TRB_TYPE_LINK) {
- LinkTrb = (LINK_TRB *) CheckedTrb;
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64) LinkTrb->PtrHi, 32));
- CheckedTrb = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
+ LinkTrb = (LINK_TRB *)CheckedTrb;
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64)LinkTrb->PtrHi, 32));
+ CheckedTrb = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));
ASSERT (CheckedTrb == Urb->Ring->RingSeg0);
}
}
@@ -1048,14 +1062,14 @@ IsTransferRingTrb ( **/
BOOLEAN
IsAsyncIntTrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN TRB_TEMPLATE *Trb,
- OUT URB **Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN TRB_TEMPLATE *Trb,
+ OUT URB **Urb
)
{
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- URB *CheckedUrb;
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ URB *CheckedUrb;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
@@ -1068,7 +1082,6 @@ IsAsyncIntTrb ( return FALSE;
}
-
/**
Check the URB's execution result and update the URB's
result accordingly.
@@ -1081,21 +1094,21 @@ IsAsyncIntTrb ( **/
BOOLEAN
XhcCheckUrbResult (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EVT_TRB_TRANSFER *EvtTrb;
- TRB_TEMPLATE *TRBPtr;
- UINTN Index;
- UINT8 TRBType;
- EFI_STATUS Status;
- URB *AsyncUrb;
- URB *CheckedUrb;
- UINT64 XhcDequeue;
- UINT32 High;
- UINT32 Low;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EVT_TRB_TRANSFER *EvtTrb;
+ TRB_TEMPLATE *TRBPtr;
+ UINTN Index;
+ UINT8 TRBType;
+ EFI_STATUS Status;
+ URB *AsyncUrb;
+ URB *CheckedUrb;
+ UINT64 XhcDequeue;
+ UINT32 High;
+ UINT32 Low;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT ((Xhc != NULL) && (Urb != NULL));
@@ -1136,8 +1149,8 @@ XhcCheckUrbResult ( //
// Need convert pci device address to host address
//
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
- TRBPtr = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32));
+ TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));
//
// Update the status of URB including the pending URB, the URB that is currently checked,
@@ -1145,7 +1158,7 @@ XhcCheckUrbResult ( // This way is used to avoid that those completed async transfer events don't get
// handled in time and are flushed by newer coming events.
//
- if (Xhc->PendingUrb != NULL && IsTransferRingTrb (Xhc, TRBPtr, Xhc->PendingUrb)) {
+ if ((Xhc->PendingUrb != NULL) && IsTransferRingTrb (Xhc, TRBPtr, Xhc->PendingUrb)) {
CheckedUrb = Xhc->PendingUrb;
} else if (IsTransferRingTrb (Xhc, TRBPtr, Urb)) {
CheckedUrb = Urb;
@@ -1159,25 +1172,25 @@ XhcCheckUrbResult ( case TRB_COMPLETION_STALL_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_STALL;
CheckedUrb->Finished = TRUE;
- DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_BABBLE_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_BABBLE;
CheckedUrb->Finished = TRUE;
- DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_DATA_BUFFER_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_BUFFER;
CheckedUrb->Finished = TRUE;
- DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_USB_TRANSACTION_ERROR:
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Finished = TRUE;
- DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n", EvtTrb->Completecode));
goto EXIT;
case TRB_COMPLETION_STOPPED:
@@ -1196,17 +1209,18 @@ XhcCheckUrbResult ( DEBUG ((DEBUG_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));
}
- TRBType = (UINT8) (TRBPtr->Type);
+ TRBType = (UINT8)(TRBPtr->Type);
if ((TRBType == TRB_TYPE_DATA_STAGE) ||
(TRBType == TRB_TYPE_NORMAL) ||
- (TRBType == TRB_TYPE_ISOCH)) {
- CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
+ (TRBType == TRB_TYPE_ISOCH))
+ {
+ CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL *)TRBPtr)->Length - EvtTrb->Length);
}
break;
default:
- DEBUG ((DEBUG_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));
+ DEBUG ((DEBUG_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n", EvtTrb->Completecode));
CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
CheckedUrb->Finished = TRUE;
goto EXIT;
@@ -1237,9 +1251,9 @@ EXIT: // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
//
- Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
- High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
- XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);
+ Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
+ High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
+ XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));
@@ -1255,7 +1269,6 @@ EXIT: return Urb->Finished;
}
-
/**
Execute the transfer by polling the URB. This is a synchronous operation.
@@ -1272,18 +1285,18 @@ EXIT: **/
EFI_STATUS
XhcExecTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN BOOLEAN CmdTransfer,
- IN URB *Urb,
- IN UINTN Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN BOOLEAN CmdTransfer,
+ IN URB *Urb,
+ IN UINTN Timeout
)
{
- EFI_STATUS Status;
- UINT8 SlotId;
- UINT8 Dci;
- BOOLEAN Finished;
- EFI_EVENT TimeoutEvent;
- BOOLEAN IndefiniteTimeout;
+ EFI_STATUS Status;
+ UINT8 SlotId;
+ UINT8 Dci;
+ BOOLEAN Finished;
+ EFI_EVENT TimeoutEvent;
+ BOOLEAN IndefiniteTimeout;
Status = EFI_SUCCESS;
Finished = FALSE;
@@ -1298,7 +1311,8 @@ XhcExecTransfer ( if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
- Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
+
+ Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
ASSERT (Dci < 32);
}
@@ -1319,9 +1333,11 @@ XhcExecTransfer ( goto DONE;
}
- Status = gBS->SetTimer (TimeoutEvent,
- TimerRelative,
- EFI_TIMER_PERIOD_MILLISECONDS(Timeout));
+ Status = gBS->SetTimer (
+ TimeoutEvent,
+ TimerRelative,
+ EFI_TIMER_PERIOD_MILLISECONDS (Timeout)
+ );
if (EFI_ERROR (Status)) {
goto DONE;
@@ -1335,17 +1351,18 @@ RINGDOORBELL: if (Finished) {
break;
}
+
gBS->Stall (XHC_1_MICROSECOND);
- } while (IndefiniteTimeout || EFI_ERROR(gBS->CheckEvent (TimeoutEvent)));
+ } while (IndefiniteTimeout || EFI_ERROR (gBS->CheckEvent (TimeoutEvent)));
DONE:
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
Urb->Result = EFI_USB_ERR_NOTEXECUTE;
} else if (!Finished) {
Urb->Result = EFI_USB_ERR_TIMEOUT;
Status = EFI_TIMEOUT;
} else if (Urb->Result != EFI_USB_NOERROR) {
- Status = EFI_DEVICE_ERROR;
+ Status = EFI_DEVICE_ERROR;
}
if (TimeoutEvent != NULL) {
@@ -1369,9 +1386,9 @@ DONE: **/
EFI_STATUS
XhciDelAsyncIntTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpNum
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpNum
)
{
LIST_ENTRY *Entry;
@@ -1389,7 +1406,8 @@ XhciDelAsyncIntTransfer ( Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
if ((Urb->Ep.BusAddr == BusAddr) &&
(Urb->Ep.EpAddr == EpNum) &&
- (Urb->Ep.Direction == Direction)) {
+ (Urb->Ep.Direction == Direction))
+ {
//
// Device doesn't finish the IntTransfer until real data comes
// So the TRB should be removed as well.
@@ -1417,13 +1435,13 @@ XhciDelAsyncIntTransfer ( **/
VOID
XhciDelAllAsyncIntTransfers (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- URB *Urb;
- EFI_STATUS Status;
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ URB *Urb;
+ EFI_STATUS Status;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
@@ -1461,18 +1479,18 @@ XhciDelAllAsyncIntTransfers ( **/
URB *
XhciInsertAsyncIntTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
)
{
- VOID *Data;
- URB *Urb;
+ VOID *Data;
+ URB *Urb;
Data = AllocateZeroPool (DataLen);
if (Data == NULL) {
@@ -1517,17 +1535,18 @@ XhciInsertAsyncIntTransfer ( **/
VOID
XhcUpdateAsyncRequest (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
if (Urb->Result == EFI_USB_NOERROR) {
Status = XhcCreateTransferTrb (Xhc, Urb);
if (EFI_ERROR (Status)) {
return;
}
+
Status = RingIntTransferDoorBell (Xhc, Urb);
if (EFI_ERROR (Status)) {
return;
@@ -1548,16 +1567,16 @@ XhcUpdateAsyncRequest ( **/
EFI_STATUS
XhcFlushAsyncIntMap (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINTN Len;
- VOID *Map;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINTN Len;
+ VOID *Map;
PciIo = Xhc->PciIo;
Len = Urb->DataLen;
@@ -1582,8 +1601,8 @@ XhcFlushAsyncIntMap ( goto ON_ERROR;
}
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
- Urb->DataMap = Map;
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
+ Urb->DataMap = Map;
return EFI_SUCCESS;
ON_ERROR:
@@ -1600,22 +1619,22 @@ ON_ERROR: VOID
EFIAPI
XhcMonitorAsyncRequests (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- USB_XHCI_INSTANCE *Xhc;
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- UINT8 *ProcBuf;
- URB *Urb;
- UINT8 SlotId;
- EFI_STATUS Status;
- EFI_TPL OldTpl;
+ USB_XHCI_INSTANCE *Xhc;
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ UINT8 *ProcBuf;
+ URB *Urb;
+ UINT8 SlotId;
+ EFI_STATUS Status;
+ EFI_TPL OldTpl;
OldTpl = gBS->RaiseTPL (XHC_TPL);
- Xhc = (USB_XHCI_INSTANCE*) Context;
+ Xhc = (USB_XHCI_INSTANCE *)Context;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
@@ -1685,7 +1704,7 @@ XhcMonitorAsyncRequests ( // his callback. Some drivers may has a lower TPL restriction.
//
gBS->RestoreTPL (OldTpl);
- (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
+ (Urb->Callback)(ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
OldTpl = gBS->RaiseTPL (XHC_TPL);
}
@@ -1713,19 +1732,19 @@ XhcMonitorAsyncRequests ( EFI_STATUS
EFIAPI
XhcPollPortStatusChange (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT8 Port,
- IN EFI_USB_PORT_STATUS *PortState
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT8 Port,
+ IN EFI_USB_PORT_STATUS *PortState
)
{
- EFI_STATUS Status;
- UINT8 Speed;
- UINT8 SlotId;
- UINT8 Retries;
- USB_DEV_ROUTE RouteChart;
+ EFI_STATUS Status;
+ UINT8 Speed;
+ UINT8 SlotId;
+ UINT8 Retries;
+ USB_DEV_ROUTE RouteChart;
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
Retries = XHC_INIT_DEVICE_SLOT_RETRIES;
if ((PortState->PortChangeStatus & (USB_PORT_STAT_C_CONNECTION | USB_PORT_STAT_C_ENABLE | USB_PORT_STAT_C_OVERCURRENT | USB_PORT_STAT_C_RESET)) == 0) {
@@ -1737,13 +1756,14 @@ XhcPollPortStatusChange ( RouteChart.Route.RootPortNum = Port + 1;
RouteChart.Route.TierNum = 1;
} else {
- if(Port < 14) {
+ if (Port < 14) {
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));
} else {
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));
}
- RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
- RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
+
+ RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
+ RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
}
SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
@@ -1756,7 +1776,8 @@ XhcPollPortStatusChange ( }
if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&
- ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {
+ ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0))
+ {
//
// Has a device attached, Identify device speed after port is enabled.
//
@@ -1796,7 +1817,6 @@ XhcPollPortStatusChange ( return Status;
}
-
/**
Calculate the device context index by endpoint address and direction.
@@ -1808,19 +1828,20 @@ XhcPollPortStatusChange ( **/
UINT8
XhcEndpointToDci (
- IN UINT8 EpAddr,
- IN UINT8 Direction
+ IN UINT8 EpAddr,
+ IN UINT8 Direction
)
{
- UINT8 Index;
+ UINT8 Index;
if (EpAddr == 0) {
return 1;
} else {
- Index = (UINT8) (2 * EpAddr);
+ Index = (UINT8)(2 * EpAddr);
if (Direction == EfiUsbDataIn) {
Index += 1;
}
+
return Index;
}
}
@@ -1846,7 +1867,8 @@ XhcBusDevAddrToSlotId ( for (Index = 0; Index < 255; Index++) {
if (Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
- (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {
+ (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr))
+ {
break;
}
}
@@ -1879,7 +1901,8 @@ XhcRouteStringToSlotId ( for (Index = 0; Index < 255; Index++) {
if (Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
- (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword))
+ {
break;
}
}
@@ -1903,12 +1926,12 @@ XhcRouteStringToSlotId ( EFI_STATUS
EFIAPI
XhcSyncEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN EVENT_RING *EvtRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN EVENT_RING *EvtRing
)
{
- UINTN Index;
- TRB_TEMPLATE *EvtTrb1;
+ UINTN Index;
+ TRB_TEMPLATE *EvtTrb1;
ASSERT (EvtRing != NULL);
@@ -1925,8 +1948,8 @@ XhcSyncEventRing ( EvtTrb1++;
- if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
- EvtTrb1 = EvtRing->EventRingSeg0;
+ if ((UINTN)EvtTrb1 >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
+ EvtTrb1 = EvtRing->EventRingSeg0;
EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
}
}
@@ -1952,12 +1975,12 @@ XhcSyncEventRing ( EFI_STATUS
EFIAPI
XhcSyncTrsRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN TRANSFER_RING *TrsRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN TRANSFER_RING *TrsRing
)
{
- UINTN Index;
- TRB_TEMPLATE *TrsTrb;
+ UINTN Index;
+ TRB_TEMPLATE *TrsTrb;
ASSERT (TrsRing != NULL);
//
@@ -1970,18 +1993,19 @@ XhcSyncTrsRing ( if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
break;
}
+
TrsTrb++;
- if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
- ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);
+ if ((UINT8)TrsTrb->Type == TRB_TYPE_LINK) {
+ ASSERT (((LINK_TRB *)TrsTrb)->TC != 0);
//
// set cycle bit in Link TRB as normal
//
- ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
+ ((LINK_TRB *)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
//
// Toggle PCS maintained by software
//
TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
- TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address
+ TrsTrb = (TRB_TEMPLATE *)TrsRing->RingSeg0; // Use host address
}
}
@@ -2018,9 +2042,9 @@ XhcSyncTrsRing ( EFI_STATUS
EFIAPI
XhcCheckNewEvent (
- IN USB_XHCI_INSTANCE *Xhc,
- IN EVENT_RING *EvtRing,
- OUT TRB_TEMPLATE **NewEvtTrb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN EVENT_RING *EvtRing,
+ OUT TRB_TEMPLATE **NewEvtTrb
)
{
ASSERT (EvtRing != NULL);
@@ -2035,7 +2059,7 @@ XhcCheckNewEvent ( //
// If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
//
- if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
+ if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
}
@@ -2055,9 +2079,9 @@ XhcCheckNewEvent ( EFI_STATUS
EFIAPI
XhcRingDoorBell (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
)
{
if (SlotId == 0) {
@@ -2080,12 +2104,12 @@ XhcRingDoorBell ( **/
EFI_STATUS
RingIntTransferDoorBell (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
)
{
- UINT8 SlotId;
- UINT8 Dci;
+ UINT8 SlotId;
+ UINT8 Dci;
SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
@@ -2108,11 +2132,11 @@ RingIntTransferDoorBell ( EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
)
{
EFI_STATUS Status;
@@ -2133,15 +2157,16 @@ XhcInitializeDeviceSlot ( CmdTrb.Type = TRB_TYPE_EN_SLOT;
Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
+
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((DEBUG_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
@@ -2159,10 +2184,10 @@ XhcInitializeDeviceSlot ( //
InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));
ASSERT (InputContext != NULL);
- ASSERT (((UINTN) InputContext & 0x3F) == 0);
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);
ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;
//
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
@@ -2183,14 +2208,15 @@ XhcInitializeDeviceSlot ( //
// The device is behind of hub device.
//
- ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);
+ ParentSlotId = XhcRouteStringToSlotId (Xhc, ParentRouteChart);
ASSERT (ParentSlotId != 0);
//
- //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
+ // if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
//
ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))
+ {
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
//
// Full/Low device attached to High speed hub port that isolates the high speed signaling
@@ -2217,9 +2243,9 @@ XhcInitializeDeviceSlot ( //
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
//
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
//
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
//
@@ -2232,6 +2258,7 @@ XhcInitializeDeviceSlot ( } else {
InputContext->EP[0].MaxPacketSize = 8;
}
+
//
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
// 1KB, and Bulk and Isoch endpoints 3KB.
@@ -2259,7 +2286,7 @@ XhcInitializeDeviceSlot ( //
OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));
ASSERT (OutputContext != NULL);
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
@@ -2271,7 +2298,7 @@ XhcInitializeDeviceSlot ( //
// Fill DCBAA with PCI device address
//
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;
//
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
@@ -2282,20 +2309,20 @@ XhcInitializeDeviceSlot ( //
gBS->Stall (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1;
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (!EFI_ERROR (Status)) {
- DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;
+ DeviceAddress = (UINT8)((DEVICE_CONTEXT *)OutputContext)->Slot.DeviceAddress;
DEBUG ((DEBUG_INFO, " Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
} else {
@@ -2321,11 +2348,11 @@ XhcInitializeDeviceSlot ( EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
)
{
EFI_STATUS Status;
@@ -2346,15 +2373,16 @@ XhcInitializeDeviceSlot64 ( CmdTrb.Type = TRB_TYPE_EN_SLOT;
Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
+
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((DEBUG_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
@@ -2372,10 +2400,10 @@ XhcInitializeDeviceSlot64 ( //
InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));
ASSERT (InputContext != NULL);
- ASSERT (((UINTN) InputContext & 0x3F) == 0);
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;
//
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
@@ -2396,14 +2424,15 @@ XhcInitializeDeviceSlot64 ( //
// The device is behind of hub device.
//
- ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);
+ ParentSlotId = XhcRouteStringToSlotId (Xhc, ParentRouteChart);
ASSERT (ParentSlotId != 0);
//
- //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
+ // if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
//
ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))
+ {
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
//
// Full/Low device attached to High speed hub port that isolates the high speed signaling
@@ -2430,9 +2459,9 @@ XhcInitializeDeviceSlot64 ( //
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
//
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
//
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
//
@@ -2445,6 +2474,7 @@ XhcInitializeDeviceSlot64 ( } else {
InputContext->EP[0].MaxPacketSize = 8;
}
+
//
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
// 1KB, and Bulk and Isoch endpoints 3KB.
@@ -2472,7 +2502,7 @@ XhcInitializeDeviceSlot64 ( //
OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));
ASSERT (OutputContext != NULL);
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
@@ -2484,7 +2514,7 @@ XhcInitializeDeviceSlot64 ( //
// Fill DCBAA with PCI device address
//
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;
//
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
@@ -2495,20 +2525,20 @@ XhcInitializeDeviceSlot64 ( //
gBS->Stall (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1;
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (!EFI_ERROR (Status)) {
- DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;
+ DeviceAddress = (UINT8)((DEVICE_CONTEXT_64 *)OutputContext)->Slot.DeviceAddress;
DEBUG ((DEBUG_INFO, " Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
} else {
@@ -2519,7 +2549,6 @@ XhcInitializeDeviceSlot64 ( return Status;
}
-
/**
Disable the specified device slot.
@@ -2532,8 +2561,8 @@ XhcInitializeDeviceSlot64 ( EFI_STATUS
EFIAPI
XhcDisableSlotCmd (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId
)
{
EFI_STATUS Status;
@@ -2549,7 +2578,8 @@ XhcDisableSlotCmd ( for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))
+ {
continue;
}
@@ -2570,16 +2600,17 @@ XhcDisableSlotCmd ( CmdTrbDisSlot.CycleBit = 1;
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
CmdTrbDisSlot.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
+
//
// Free the slot's device context entry
//
@@ -2594,6 +2625,7 @@ XhcDisableSlotCmd ( if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
+
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
}
@@ -2616,6 +2648,7 @@ XhcDisableSlotCmd ( if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));
}
+
//
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
@@ -2639,8 +2672,8 @@ XhcDisableSlotCmd ( EFI_STATUS
EFIAPI
XhcDisableSlotCmd64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId
)
{
EFI_STATUS Status;
@@ -2656,7 +2689,8 @@ XhcDisableSlotCmd64 ( for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))
+ {
continue;
}
@@ -2677,16 +2711,17 @@ XhcDisableSlotCmd64 ( CmdTrbDisSlot.CycleBit = 1;
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
CmdTrbDisSlot.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
+
//
// Free the slot's device context entry
//
@@ -2701,6 +2736,7 @@ XhcDisableSlotCmd64 ( if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
+
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
}
@@ -2721,8 +2757,9 @@ XhcDisableSlotCmd64 ( }
if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
- UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
+ UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
}
+
//
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
@@ -2749,23 +2786,23 @@ XhcDisableSlotCmd64 ( UINT8
EFIAPI
XhcInitializeEndpointContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN INPUT_CONTEXT *InputContext,
- IN USB_INTERFACE_DESCRIPTOR *IfDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN INPUT_CONTEXT *InputContext,
+ IN USB_INTERFACE_DESCRIPTOR *IfDesc
)
{
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- UINT8 Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINT8 Interval;
- TRANSFER_RING *EndpointTransferRing;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ UINT8 Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINT8 Interval;
+ TRANSFER_RING *EndpointTransferRing;
MaxDci = 0;
@@ -2815,14 +2852,16 @@ XhcInitializeEndpointContext ( InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
- DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created BULK ring [%p~%p)\n",
- EpDesc->EndpointAddress,
- EndpointTransferRing->RingSeg0,
- (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
- ));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((
+ DEBUG_INFO,
+ "Endpoint[%x]: Created BULK ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
break;
@@ -2834,6 +2873,7 @@ XhcInitializeEndpointContext ( InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
}
+
//
// Get the bInterval from descriptor and init the the interval field of endpoint context.
// Refer to XHCI 1.1 spec section 6.2.3.6.
@@ -2862,6 +2902,7 @@ XhcInitializeEndpointContext ( InputContext->EP[Dci-1].CErr = 3;
InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
}
+
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
//
@@ -2873,7 +2914,7 @@ XhcInitializeEndpointContext ( // Calculate through the bInterval field of Endpoint descriptor.
//
ASSERT (Interval != 0);
- InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;
} else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
Interval = EpDesc->Interval;
ASSERT (Interval >= 1 && Interval <= 16);
@@ -2888,15 +2929,18 @@ XhcInitializeEndpointContext ( }
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
- DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created INT ring [%p~%p)\n",
- EpDesc->EndpointAddress,
- EndpointTransferRing->RingSeg0,
- (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
- ));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((
+ DEBUG_INFO,
+ "Endpoint[%x]: Created INT ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
+
break;
case USB_ENDPOINT_CONTROL:
@@ -2915,8 +2959,8 @@ XhcInitializeEndpointContext ( ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
- PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
- PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
+ PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
@@ -2941,23 +2985,23 @@ XhcInitializeEndpointContext ( UINT8
EFIAPI
XhcInitializeEndpointContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN INPUT_CONTEXT_64 *InputContext,
- IN USB_INTERFACE_DESCRIPTOR *IfDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN INPUT_CONTEXT_64 *InputContext,
+ IN USB_INTERFACE_DESCRIPTOR *IfDesc
)
{
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- UINT8 Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINT8 Interval;
- TRANSFER_RING *EndpointTransferRing;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ UINT8 Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINT8 Interval;
+ TRANSFER_RING *EndpointTransferRing;
MaxDci = 0;
@@ -3007,14 +3051,16 @@ XhcInitializeEndpointContext64 ( InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
- DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created BULK ring [%p~%p)\n",
- EpDesc->EndpointAddress,
- EndpointTransferRing->RingSeg0,
- (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
- ));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((
+ DEBUG_INFO,
+ "Endpoint64[%x]: Created BULK ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
break;
@@ -3026,6 +3072,7 @@ XhcInitializeEndpointContext64 ( InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
}
+
//
// Get the bInterval from descriptor and init the the interval field of endpoint context.
// Refer to XHCI 1.1 spec section 6.2.3.6.
@@ -3054,6 +3101,7 @@ XhcInitializeEndpointContext64 ( InputContext->EP[Dci-1].CErr = 3;
InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
}
+
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
//
@@ -3065,7 +3113,7 @@ XhcInitializeEndpointContext64 ( // Calculate through the bInterval field of Endpoint descriptor.
//
ASSERT (Interval != 0);
- InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;
} else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
Interval = EpDesc->Interval;
ASSERT (Interval >= 1 && Interval <= 16);
@@ -3080,15 +3128,18 @@ XhcInitializeEndpointContext64 ( }
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
- DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created INT ring [%p~%p)\n",
- EpDesc->EndpointAddress,
- EndpointTransferRing->RingSeg0,
- (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
- ));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ CreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((
+ DEBUG_INFO,
+ "Endpoint64[%x]: Created INT ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN)EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
+
break;
case USB_ENDPOINT_CONTROL:
@@ -3107,8 +3158,8 @@ XhcInitializeEndpointContext64 ( ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
- PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
- PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
+ PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
@@ -3132,23 +3183,24 @@ XhcInitializeEndpointContext64 ( EFI_STATUS
EFIAPI
XhcSetConfigCmd (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- UINT8 Index;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ UINT8 Index;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
INPUT_CONTEXT *InputContext;
DEVICE_CONTEXT *OutputContext;
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+
//
// 4.6.6 Configure Endpoint
//
@@ -3186,7 +3238,7 @@ XhcSetConfigCmd ( // configure endpoint
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -3195,9 +3247,9 @@ XhcSetConfigCmd ( DEBUG ((DEBUG_INFO, "Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
@@ -3222,23 +3274,24 @@ XhcSetConfigCmd ( EFI_STATUS
EFIAPI
XhcSetConfigCmd64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- UINT8 Index;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ UINT8 Index;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
INPUT_CONTEXT_64 *InputContext;
DEVICE_CONTEXT_64 *OutputContext;
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+
//
// 4.6.6 Configure Endpoint
//
@@ -3276,7 +3329,7 @@ XhcSetConfigCmd64 ( // configure endpoint
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -3285,9 +3338,9 @@ XhcSetConfigCmd64 ( DEBUG ((DEBUG_INFO, "Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
@@ -3313,15 +3366,15 @@ XhcSetConfigCmd64 ( EFI_STATUS
EFIAPI
XhcStopEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *PendingUrb OPTIONAL
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *PendingUrb OPTIONAL
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
DEBUG ((DEBUG_INFO, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
@@ -3356,13 +3409,13 @@ XhcStopEndpoint ( CmdTrbStopED.Type = TRB_TYPE_STOP_ENDPOINT;
CmdTrbStopED.EDID = Dci;
CmdTrbStopED.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbStopED,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbStopED,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
}
@@ -3385,9 +3438,9 @@ XhcStopEndpoint ( EFI_STATUS
EFIAPI
XhcResetEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
)
{
EFI_STATUS Status;
@@ -3404,13 +3457,13 @@ XhcResetEndpoint ( CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;
CmdTrbResetED.EDID = Dci;
CmdTrbResetED.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbResetED,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
}
@@ -3433,10 +3486,10 @@ XhcResetEndpoint ( EFI_STATUS
EFIAPI
XhcSetTrDequeuePointer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *Urb
)
{
EFI_STATUS Status;
@@ -3450,20 +3503,20 @@ XhcSetTrDequeuePointer ( // Send stop endpoint command to transit Endpoint from running to stop state
//
ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdSetTRDeq.CycleBit = 1;
CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;
CmdSetTRDeq.Endpoint = Dci;
CmdSetTRDeq.SlotId = SlotId;
- Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
+ Status = XhcCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdSetTRDeq,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
}
@@ -3485,26 +3538,26 @@ XhcSetTrDequeuePointer ( EFI_STATUS
EFIAPI
XhcSetInterface (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
- IN EFI_USB_DEVICE_REQUEST *Request
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
+ IN EFI_USB_DEVICE_REQUEST *Request
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDescActive;
- USB_INTERFACE_DESCRIPTOR *IfDescSet;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- UINT8 Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *RingSeg;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDescActive;
+ USB_INTERFACE_DESCRIPTOR *IfDescSet;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ UINT8 Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *RingSeg;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
INPUT_CONTEXT *InputContext;
@@ -3533,18 +3586,18 @@ XhcSetInterface ( MaxDci = 0;
IfDescActive = NULL;
- IfDescSet = NULL;
+ IfDescSet = NULL;
IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
- while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {
+ while ((UINTN)IfDesc < ((UINTN)ConfigDesc + ConfigDesc->TotalLength)) {
if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {
- if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {
+ if (IfDesc->InterfaceNumber == (UINT8)Request->Index) {
if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {
//
// Find out the active interface descriptor.
//
IfDescActive = IfDesc;
- } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {
+ } else if (IfDesc->AlternateSetting == (UINT8)Request->Value) {
//
// Find out the interface descriptor to set.
//
@@ -3552,6 +3605,7 @@ XhcSetInterface ( }
}
}
+
IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
@@ -3570,8 +3624,8 @@ XhcSetInterface ( //
if ((IfDescActive != NULL) && (IfDescSet != NULL)) {
- NumEp = IfDescActive->NumEndpoints;
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);
+ NumEp = IfDescActive->NumEndpoints;
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDescActive + 1);
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
@@ -3582,14 +3636,15 @@ XhcSetInterface ( continue;
}
- EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
- Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
Dci = XhcEndpointToDci (EpAddr, Direction);
ASSERT (Dci < 32);
if (Dci > MaxDci) {
MaxDci = Dci;
}
+
//
// XHCI 4.3.6 - Setting Alternate Interfaces
// 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
@@ -3598,6 +3653,7 @@ XhcSetInterface ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// XHCI 4.3.6 - Setting Alternate Interfaces
// 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
@@ -3607,6 +3663,7 @@ XhcSetInterface ( if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
+
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;
}
@@ -3646,7 +3703,7 @@ XhcSetInterface ( // 5) Issue and successfully complete a Configure Endpoint Command.
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -3655,9 +3712,9 @@ XhcSetInterface ( DEBUG ((DEBUG_INFO, "SetInterface: Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));
@@ -3665,7 +3722,7 @@ XhcSetInterface ( //
// Update the active AlternateSetting.
//
- Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;
+ Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8)Request->Index] = (UINT8)Request->Value;
}
}
@@ -3687,26 +3744,26 @@ XhcSetInterface ( EFI_STATUS
EFIAPI
XhcSetInterface64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
- IN EFI_USB_DEVICE_REQUEST *Request
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
+ IN EFI_USB_DEVICE_REQUEST *Request
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDescActive;
- USB_INTERFACE_DESCRIPTOR *IfDescSet;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- UINT8 Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *RingSeg;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDescActive;
+ USB_INTERFACE_DESCRIPTOR *IfDescSet;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ UINT8 Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *RingSeg;
CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
INPUT_CONTEXT_64 *InputContext;
@@ -3735,18 +3792,18 @@ XhcSetInterface64 ( MaxDci = 0;
IfDescActive = NULL;
- IfDescSet = NULL;
+ IfDescSet = NULL;
IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
- while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {
+ while ((UINTN)IfDesc < ((UINTN)ConfigDesc + ConfigDesc->TotalLength)) {
if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {
- if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {
+ if (IfDesc->InterfaceNumber == (UINT8)Request->Index) {
if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {
//
// Find out the active interface descriptor.
//
IfDescActive = IfDesc;
- } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {
+ } else if (IfDesc->AlternateSetting == (UINT8)Request->Value) {
//
// Find out the interface descriptor to set.
//
@@ -3754,6 +3811,7 @@ XhcSetInterface64 ( }
}
}
+
IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
@@ -3772,8 +3830,8 @@ XhcSetInterface64 ( //
if ((IfDescActive != NULL) && (IfDescSet != NULL)) {
- NumEp = IfDescActive->NumEndpoints;
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);
+ NumEp = IfDescActive->NumEndpoints;
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDescActive + 1);
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
@@ -3784,14 +3842,15 @@ XhcSetInterface64 ( continue;
}
- EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
- Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
Dci = XhcEndpointToDci (EpAddr, Direction);
ASSERT (Dci < 32);
if (Dci > MaxDci) {
MaxDci = Dci;
}
+
//
// XHCI 4.3.6 - Setting Alternate Interfaces
// 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
@@ -3800,6 +3859,7 @@ XhcSetInterface64 ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// XHCI 4.3.6 - Setting Alternate Interfaces
// 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
@@ -3809,6 +3869,7 @@ XhcSetInterface64 ( if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
+
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;
}
@@ -3848,7 +3909,7 @@ XhcSetInterface64 ( // 5) Issue and successfully complete a Configure Endpoint Command.
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -3857,9 +3918,9 @@ XhcSetInterface64 ( DEBUG ((DEBUG_INFO, "SetInterface64: Configure Endpoint\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));
@@ -3867,7 +3928,7 @@ XhcSetInterface64 ( //
// Update the active AlternateSetting.
//
- Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;
+ Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8)Request->Index] = (UINT8)Request->Value;
}
}
@@ -3887,9 +3948,9 @@ XhcSetInterface64 ( EFI_STATUS
EFIAPI
XhcEvaluateContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
)
{
EFI_STATUS Status;
@@ -3910,7 +3971,7 @@ XhcEvaluateContext ( InputContext->EP[0].MaxPacketSize = MaxPacketSize;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1;
@@ -3919,13 +3980,14 @@ XhcEvaluateContext ( DEBUG ((DEBUG_INFO, "Evaluate context\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -3942,9 +4004,9 @@ XhcEvaluateContext ( EFI_STATUS
EFIAPI
XhcEvaluateContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
)
{
EFI_STATUS Status;
@@ -3965,7 +4027,7 @@ XhcEvaluateContext64 ( InputContext->EP[0].MaxPacketSize = MaxPacketSize;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1;
@@ -3974,17 +4036,17 @@ XhcEvaluateContext64 ( DEBUG ((DEBUG_INFO, "Evaluate context\n"));
Status = XhcCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
}
+
return Status;
}
-
/**
Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
@@ -3999,11 +4061,11 @@ XhcEvaluateContext64 ( **/
EFI_STATUS
XhcConfigHubContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
)
{
EFI_STATUS Status;
@@ -4027,14 +4089,14 @@ XhcConfigHubContext ( //
// Copy the slot context from OutputContext to Input context
//
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
InputContext->Slot.Hub = 1;
InputContext->Slot.PortNum = PortNum;
InputContext->Slot.TTT = TTT;
InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -4042,14 +4104,15 @@ XhcConfigHubContext ( CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -4067,11 +4130,11 @@ XhcConfigHubContext ( **/
EFI_STATUS
XhcConfigHubContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
)
{
EFI_STATUS Status;
@@ -4095,14 +4158,14 @@ XhcConfigHubContext64 ( //
// Copy the slot context from OutputContext to Input context
//
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
InputContext->Slot.Hub = 1;
InputContext->Slot.PortNum = PortNum;
InputContext->Slot.TTT = TTT;
InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -4110,13 +4173,14 @@ XhcConfigHubContext64 ( CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
}
+
return Status;
}
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h index 3f9cdb1..7c85f79 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h @@ -10,73 +10,73 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_XHCI_SCHED_H_
#define _EFI_XHCI_SCHED_H_
-#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
-#define XHC_INIT_DEVICE_SLOT_RETRIES 1
+#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
+#define XHC_INIT_DEVICE_SLOT_RETRIES 1
//
// Transfer types, used in URB to identify the transfer type
//
-#define XHC_CTRL_TRANSFER 0x01
-#define XHC_BULK_TRANSFER 0x02
-#define XHC_INT_TRANSFER_SYNC 0x04
-#define XHC_INT_TRANSFER_ASYNC 0x08
-#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
+#define XHC_CTRL_TRANSFER 0x01
+#define XHC_BULK_TRANSFER 0x02
+#define XHC_INT_TRANSFER_SYNC 0x04
+#define XHC_INT_TRANSFER_ASYNC 0x08
+#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
//
// 6.4.6 TRB Types
//
-#define TRB_TYPE_NORMAL 1
-#define TRB_TYPE_SETUP_STAGE 2
-#define TRB_TYPE_DATA_STAGE 3
-#define TRB_TYPE_STATUS_STAGE 4
-#define TRB_TYPE_ISOCH 5
-#define TRB_TYPE_LINK 6
-#define TRB_TYPE_EVENT_DATA 7
-#define TRB_TYPE_NO_OP 8
-#define TRB_TYPE_EN_SLOT 9
-#define TRB_TYPE_DIS_SLOT 10
-#define TRB_TYPE_ADDRESS_DEV 11
-#define TRB_TYPE_CON_ENDPOINT 12
-#define TRB_TYPE_EVALU_CONTXT 13
-#define TRB_TYPE_RESET_ENDPOINT 14
-#define TRB_TYPE_STOP_ENDPOINT 15
-#define TRB_TYPE_SET_TR_DEQUE 16
-#define TRB_TYPE_RESET_DEV 17
-#define TRB_TYPE_GET_PORT_BANW 21
-#define TRB_TYPE_FORCE_HEADER 22
-#define TRB_TYPE_NO_OP_COMMAND 23
-#define TRB_TYPE_TRANS_EVENT 32
-#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
-#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
-#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
-#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
-#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
+#define TRB_TYPE_NORMAL 1
+#define TRB_TYPE_SETUP_STAGE 2
+#define TRB_TYPE_DATA_STAGE 3
+#define TRB_TYPE_STATUS_STAGE 4
+#define TRB_TYPE_ISOCH 5
+#define TRB_TYPE_LINK 6
+#define TRB_TYPE_EVENT_DATA 7
+#define TRB_TYPE_NO_OP 8
+#define TRB_TYPE_EN_SLOT 9
+#define TRB_TYPE_DIS_SLOT 10
+#define TRB_TYPE_ADDRESS_DEV 11
+#define TRB_TYPE_CON_ENDPOINT 12
+#define TRB_TYPE_EVALU_CONTXT 13
+#define TRB_TYPE_RESET_ENDPOINT 14
+#define TRB_TYPE_STOP_ENDPOINT 15
+#define TRB_TYPE_SET_TR_DEQUE 16
+#define TRB_TYPE_RESET_DEV 17
+#define TRB_TYPE_GET_PORT_BANW 21
+#define TRB_TYPE_FORCE_HEADER 22
+#define TRB_TYPE_NO_OP_COMMAND 23
+#define TRB_TYPE_TRANS_EVENT 32
+#define TRB_TYPE_COMMAND_COMPLT_EVENT 33
+#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
+#define TRB_TYPE_HOST_CONTROLLER_EVENT 37
+#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
+#define TRB_TYPE_MFINDEX_WRAP_EVENT 39
//
// Endpoint Type (EP Type).
//
-#define ED_NOT_VALID 0
-#define ED_ISOCH_OUT 1
-#define ED_BULK_OUT 2
-#define ED_INTERRUPT_OUT 3
-#define ED_CONTROL_BIDIR 4
-#define ED_ISOCH_IN 5
-#define ED_BULK_IN 6
-#define ED_INTERRUPT_IN 7
+#define ED_NOT_VALID 0
+#define ED_ISOCH_OUT 1
+#define ED_BULK_OUT 2
+#define ED_INTERRUPT_OUT 3
+#define ED_CONTROL_BIDIR 4
+#define ED_ISOCH_IN 5
+#define ED_BULK_IN 6
+#define ED_INTERRUPT_IN 7
//
// 6.4.5 TRB Completion Codes
//
-#define TRB_COMPLETION_INVALID 0
-#define TRB_COMPLETION_SUCCESS 1
-#define TRB_COMPLETION_DATA_BUFFER_ERROR 2
-#define TRB_COMPLETION_BABBLE_ERROR 3
-#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
-#define TRB_COMPLETION_TRB_ERROR 5
-#define TRB_COMPLETION_STALL_ERROR 6
-#define TRB_COMPLETION_SHORT_PACKET 13
-#define TRB_COMPLETION_STOPPED 26
-#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27
+#define TRB_COMPLETION_INVALID 0
+#define TRB_COMPLETION_SUCCESS 1
+#define TRB_COMPLETION_DATA_BUFFER_ERROR 2
+#define TRB_COMPLETION_BABBLE_ERROR 3
+#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
+#define TRB_COMPLETION_TRB_ERROR 5
+#define TRB_COMPLETION_STALL_ERROR 6
+#define TRB_COMPLETION_SHORT_PACKET 13
+#define TRB_COMPLETION_STOPPED 26
+#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27
//
// The topology string used to present usb device location
@@ -85,15 +85,15 @@ typedef struct _USB_DEV_TOPOLOGY { //
// The tier concatenation of down stream port.
//
- UINT32 RouteString:20;
+ UINT32 RouteString : 20;
//
// The root port number of the chain.
//
- UINT32 RootPortNum:8;
+ UINT32 RootPortNum : 8;
//
// The Tier the device reside.
//
- UINT32 TierNum:4;
+ UINT32 TierNum : 4;
} USB_DEV_TOPOLOGY;
//
@@ -126,33 +126,33 @@ typedef struct _USB_ENDPOINT { // TRB Template
//
typedef struct _TRB_TEMPLATE {
- UINT32 Parameter1;
+ UINT32 Parameter1;
- UINT32 Parameter2;
+ UINT32 Parameter2;
- UINT32 Status;
+ UINT32 Status;
- UINT32 CycleBit:1;
- UINT32 RsvdZ1:9;
- UINT32 Type:6;
- UINT32 Control:16;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ1 : 9;
+ UINT32 Type : 6;
+ UINT32 Control : 16;
} TRB_TEMPLATE;
typedef struct _TRANSFER_RING {
- VOID *RingSeg0;
- UINTN TrbNumber;
- TRB_TEMPLATE *RingEnqueue;
- TRB_TEMPLATE *RingDequeue;
- UINT32 RingPCS;
+ VOID *RingSeg0;
+ UINTN TrbNumber;
+ TRB_TEMPLATE *RingEnqueue;
+ TRB_TEMPLATE *RingDequeue;
+ UINT32 RingPCS;
} TRANSFER_RING;
typedef struct _EVENT_RING {
- VOID *ERSTBase;
- VOID *EventRingSeg0;
- UINTN TrbNumber;
- TRB_TEMPLATE *EventRingEnqueue;
- TRB_TEMPLATE *EventRingDequeue;
- UINT32 EventRingCCS;
+ VOID *ERSTBase;
+ VOID *EventRingSeg0;
+ UINTN TrbNumber;
+ TRB_TEMPLATE *EventRingEnqueue;
+ TRB_TEMPLATE *EventRingDequeue;
+ UINT32 EventRingCCS;
} EVENT_RING;
//
@@ -160,39 +160,39 @@ typedef struct _EVENT_RING { // usb requests.
//
typedef struct _URB {
- UINT32 Signature;
- LIST_ENTRY UrbList;
+ UINT32 Signature;
+ LIST_ENTRY UrbList;
//
// Usb Device URB related information
//
- USB_ENDPOINT Ep;
- EFI_USB_DEVICE_REQUEST *Request;
- VOID *Data;
- UINTN DataLen;
- VOID *DataPhy;
- VOID *DataMap;
- EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
- VOID *Context;
+ USB_ENDPOINT Ep;
+ EFI_USB_DEVICE_REQUEST *Request;
+ VOID *Data;
+ UINTN DataLen;
+ VOID *DataPhy;
+ VOID *DataMap;
+ EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
+ VOID *Context;
//
// Execute result
//
- UINT32 Result;
+ UINT32 Result;
//
// completed data length
//
- UINTN Completed;
+ UINTN Completed;
//
// Command/Tranfer Ring info
//
- TRANSFER_RING *Ring;
- TRB_TEMPLATE *TrbStart;
- TRB_TEMPLATE *TrbEnd;
- UINTN TrbNum;
- BOOLEAN StartDone;
- BOOLEAN EndDone;
- BOOLEAN Finished;
-
- TRB_TEMPLATE *EvtTrb;
+ TRANSFER_RING *Ring;
+ TRB_TEMPLATE *TrbStart;
+ TRB_TEMPLATE *TrbEnd;
+ UINTN TrbNum;
+ BOOLEAN StartDone;
+ BOOLEAN EndDone;
+ BOOLEAN Finished;
+
+ TRB_TEMPLATE *EvtTrb;
} URB;
//
@@ -203,11 +203,11 @@ typedef struct _URB { // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
//
typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
- UINT32 PtrLo;
- UINT32 PtrHi;
- UINT32 RingTrbSize:16;
- UINT32 RsvdZ1:16;
- UINT32 RsvdZ2;
+ UINT32 PtrLo;
+ UINT32 PtrHi;
+ UINT32 RingTrbSize : 16;
+ UINT32 RsvdZ1 : 16;
+ UINT32 RsvdZ2;
} EVENT_RING_SEG_TABLE_ENTRY;
//
@@ -217,25 +217,25 @@ typedef struct _EVENT_RING_SEG_TABLE_ENTRY { // Rings, and to define the Data stage information for Control Transfer Rings.
//
typedef struct _TRANSFER_TRB_NORMAL {
- UINT32 TRBPtrLo;
-
- UINT32 TRBPtrHi;
-
- UINT32 Length:17;
- UINT32 TDSize:5;
- UINT32 IntTarget:10;
-
- UINT32 CycleBit:1;
- UINT32 ENT:1;
- UINT32 ISP:1;
- UINT32 NS:1;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 IDT:1;
- UINT32 RsvdZ1:2;
- UINT32 BEI:1;
- UINT32 Type:6;
- UINT32 RsvdZ2:16;
+ UINT32 TRBPtrLo;
+
+ UINT32 TRBPtrHi;
+
+ UINT32 Length : 17;
+ UINT32 TDSize : 5;
+ UINT32 IntTarget : 10;
+
+ UINT32 CycleBit : 1;
+ UINT32 ENT : 1;
+ UINT32 ISP : 1;
+ UINT32 NS : 1;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 IDT : 1;
+ UINT32 RsvdZ1 : 2;
+ UINT32 BEI : 1;
+ UINT32 Type : 6;
+ UINT32 RsvdZ2 : 16;
} TRANSFER_TRB_NORMAL;
//
@@ -243,25 +243,25 @@ typedef struct _TRANSFER_TRB_NORMAL { // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
//
typedef struct _TRANSFER_TRB_CONTROL_SETUP {
- UINT32 bmRequestType:8;
- UINT32 bRequest:8;
- UINT32 wValue:16;
-
- UINT32 wIndex:16;
- UINT32 wLength:16;
-
- UINT32 Length:17;
- UINT32 RsvdZ1:5;
- UINT32 IntTarget:10;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:4;
- UINT32 IOC:1;
- UINT32 IDT:1;
- UINT32 RsvdZ3:3;
- UINT32 Type:6;
- UINT32 TRT:2;
- UINT32 RsvdZ4:14;
+ UINT32 bmRequestType : 8;
+ UINT32 bRequest : 8;
+ UINT32 wValue : 16;
+
+ UINT32 wIndex : 16;
+ UINT32 wLength : 16;
+
+ UINT32 Length : 17;
+ UINT32 RsvdZ1 : 5;
+ UINT32 IntTarget : 10;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 4;
+ UINT32 IOC : 1;
+ UINT32 IDT : 1;
+ UINT32 RsvdZ3 : 3;
+ UINT32 Type : 6;
+ UINT32 TRT : 2;
+ UINT32 RsvdZ4 : 14;
} TRANSFER_TRB_CONTROL_SETUP;
//
@@ -269,25 +269,25 @@ typedef struct _TRANSFER_TRB_CONTROL_SETUP { // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
//
typedef struct _TRANSFER_TRB_CONTROL_DATA {
- UINT32 TRBPtrLo;
-
- UINT32 TRBPtrHi;
-
- UINT32 Length:17;
- UINT32 TDSize:5;
- UINT32 IntTarget:10;
-
- UINT32 CycleBit:1;
- UINT32 ENT:1;
- UINT32 ISP:1;
- UINT32 NS:1;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 IDT:1;
- UINT32 RsvdZ1:3;
- UINT32 Type:6;
- UINT32 DIR:1;
- UINT32 RsvdZ2:15;
+ UINT32 TRBPtrLo;
+
+ UINT32 TRBPtrHi;
+
+ UINT32 Length : 17;
+ UINT32 TDSize : 5;
+ UINT32 IntTarget : 10;
+
+ UINT32 CycleBit : 1;
+ UINT32 ENT : 1;
+ UINT32 ISP : 1;
+ UINT32 NS : 1;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 IDT : 1;
+ UINT32 RsvdZ1 : 3;
+ UINT32 Type : 6;
+ UINT32 DIR : 1;
+ UINT32 RsvdZ2 : 15;
} TRANSFER_TRB_CONTROL_DATA;
//
@@ -295,21 +295,21 @@ typedef struct _TRANSFER_TRB_CONTROL_DATA { // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
//
typedef struct _TRANSFER_TRB_CONTROL_STATUS {
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 RsvdZ3:22;
- UINT32 IntTarget:10;
-
- UINT32 CycleBit:1;
- UINT32 ENT:1;
- UINT32 RsvdZ4:2;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 RsvdZ5:4;
- UINT32 Type:6;
- UINT32 DIR:1;
- UINT32 RsvdZ6:15;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 RsvdZ3 : 22;
+ UINT32 IntTarget : 10;
+
+ UINT32 CycleBit : 1;
+ UINT32 ENT : 1;
+ UINT32 RsvdZ4 : 2;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 RsvdZ5 : 4;
+ UINT32 Type : 6;
+ UINT32 DIR : 1;
+ UINT32 RsvdZ6 : 15;
} TRANSFER_TRB_CONTROL_STATUS;
//
@@ -318,21 +318,21 @@ typedef struct _TRANSFER_TRB_CONTROL_STATUS { // for more information on the use and operation of Transfer Events.
//
typedef struct _EVT_TRB_TRANSFER {
- UINT32 TRBPtrLo;
+ UINT32 TRBPtrLo;
- UINT32 TRBPtrHi;
+ UINT32 TRBPtrHi;
- UINT32 Length:24;
- UINT32 Completecode:8;
+ UINT32 Length : 24;
+ UINT32 Completecode : 8;
- UINT32 CycleBit:1;
- UINT32 RsvdZ1:1;
- UINT32 ED:1;
- UINT32 RsvdZ2:7;
- UINT32 Type:6;
- UINT32 EndpointId:5;
- UINT32 RsvdZ3:3;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ1 : 1;
+ UINT32 ED : 1;
+ UINT32 RsvdZ2 : 7;
+ UINT32 Type : 6;
+ UINT32 EndpointId : 5;
+ UINT32 RsvdZ3 : 3;
+ UINT32 SlotId : 8;
} EVT_TRB_TRANSFER;
//
@@ -341,26 +341,26 @@ typedef struct _EVT_TRB_TRANSFER { // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
//
typedef struct _EVT_TRB_COMMAND_COMPLETION {
- UINT32 TRBPtrLo;
+ UINT32 TRBPtrLo;
- UINT32 TRBPtrHi;
+ UINT32 TRBPtrHi;
- UINT32 RsvdZ2:24;
- UINT32 Completecode:8;
+ UINT32 RsvdZ2 : 24;
+ UINT32 Completecode : 8;
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 VFID:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 VFID : 8;
+ UINT32 SlotId : 8;
} EVT_TRB_COMMAND_COMPLETION;
typedef union _TRB {
- TRB_TEMPLATE TrbTemplate;
- TRANSFER_TRB_NORMAL TrbNormal;
- TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
- TRANSFER_TRB_CONTROL_DATA TrbCtrData;
- TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
+ TRB_TEMPLATE TrbTemplate;
+ TRANSFER_TRB_NORMAL TrbNormal;
+ TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
+ TRANSFER_TRB_CONTROL_DATA TrbCtrData;
+ TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
} TRB;
//
@@ -369,14 +369,14 @@ typedef union _TRB { // mechanisms offered by the xHCI.
//
typedef struct _CMD_TRB_NO_OP {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 RsvdZ4:16;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 16;
} CMD_TRB_NO_OP;
//
@@ -385,14 +385,14 @@ typedef struct _CMD_TRB_NO_OP { // selected slot to the host in a Command Completion Event.
//
typedef struct _CMD_TRB_ENABLE_SLOT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 RsvdZ4:16;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 16;
} CMD_TRB_ENABLE_SLOT;
//
@@ -401,15 +401,15 @@ typedef struct _CMD_TRB_ENABLE_SLOT { // internal xHC resources assigned to the slot.
//
typedef struct _CMD_TRB_DISABLE_SLOT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 RsvdZ4:8;
- UINT32 SlotId:8;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_DISABLE_SLOT;
//
@@ -419,18 +419,18 @@ typedef struct _CMD_TRB_DISABLE_SLOT { // issue a SET_ADDRESS request to the USB device.
//
typedef struct _CMD_TRB_ADDRESS_DEVICE {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1;
+ UINT32 RsvdZ1;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:8;
- UINT32 BSR:1;
- UINT32 Type:6;
- UINT32 RsvdZ3:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 8;
+ UINT32 BSR : 1;
+ UINT32 Type : 6;
+ UINT32 RsvdZ3 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_ADDRESS_DEVICE;
//
@@ -439,18 +439,18 @@ typedef struct _CMD_TRB_ADDRESS_DEVICE { // endpoints selected by the command.
//
typedef struct _CMD_TRB_CONFIG_ENDPOINT {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1;
+ UINT32 RsvdZ1;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:8;
- UINT32 DC:1;
- UINT32 Type:6;
- UINT32 RsvdZ3:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 8;
+ UINT32 DC : 1;
+ UINT32 Type : 6;
+ UINT32 RsvdZ3 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_CONFIG_ENDPOINT;
//
@@ -460,17 +460,17 @@ typedef struct _CMD_TRB_CONFIG_ENDPOINT { // shall evaluate any changes
//
typedef struct _CMD_TRB_EVALUATE_CONTEXT {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1;
+ UINT32 RsvdZ1;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:9;
- UINT32 Type:6;
- UINT32 RsvdZ3:8;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 9;
+ UINT32 Type : 6;
+ UINT32 RsvdZ3 : 8;
+ UINT32 SlotId : 8;
} CMD_TRB_EVALUATE_CONTEXT;
//
@@ -478,17 +478,17 @@ typedef struct _CMD_TRB_EVALUATE_CONTEXT { // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
//
typedef struct _CMD_TRB_RESET_ENDPOINT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:8;
- UINT32 TSP:1;
- UINT32 Type:6;
- UINT32 EDID:5;
- UINT32 RsvdZ4:3;
- UINT32 SlotId:8;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 8;
+ UINT32 TSP : 1;
+ UINT32 Type : 6;
+ UINT32 EDID : 5;
+ UINT32 RsvdZ4 : 3;
+ UINT32 SlotId : 8;
} CMD_TRB_RESET_ENDPOINT;
//
@@ -497,17 +497,17 @@ typedef struct _CMD_TRB_RESET_ENDPOINT { // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
//
typedef struct _CMD_TRB_STOP_ENDPOINT {
- UINT32 RsvdZ0;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
-
- UINT32 CycleBit:1;
- UINT32 RsvdZ3:9;
- UINT32 Type:6;
- UINT32 EDID:5;
- UINT32 RsvdZ4:2;
- UINT32 SP:1;
- UINT32 SlotId:8;
+ UINT32 RsvdZ0;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ3 : 9;
+ UINT32 Type : 6;
+ UINT32 EDID : 5;
+ UINT32 RsvdZ4 : 2;
+ UINT32 SP : 1;
+ UINT32 SlotId : 8;
} CMD_TRB_STOP_ENDPOINT;
//
@@ -516,19 +516,19 @@ typedef struct _CMD_TRB_STOP_ENDPOINT { // Pointer and DCS fields of an Endpoint or Stream Context.
//
typedef struct _CMD_SET_TR_DEQ_POINTER {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1:16;
- UINT32 StreamID:16;
+ UINT32 RsvdZ1 : 16;
+ UINT32 StreamID : 16;
- UINT32 CycleBit:1;
- UINT32 RsvdZ2:9;
- UINT32 Type:6;
- UINT32 Endpoint:5;
- UINT32 RsvdZ3:3;
- UINT32 SlotId:8;
+ UINT32 CycleBit : 1;
+ UINT32 RsvdZ2 : 9;
+ UINT32 Type : 6;
+ UINT32 Endpoint : 5;
+ UINT32 RsvdZ3 : 3;
+ UINT32 SlotId : 8;
} CMD_SET_TR_DEQ_POINTER;
//
@@ -536,211 +536,207 @@ typedef struct _CMD_SET_TR_DEQ_POINTER { // A Link TRB provides support for non-contiguous TRB Rings.
//
typedef struct _LINK_TRB {
- UINT32 PtrLo;
+ UINT32 PtrLo;
- UINT32 PtrHi;
+ UINT32 PtrHi;
- UINT32 RsvdZ1:22;
- UINT32 InterTarget:10;
+ UINT32 RsvdZ1 : 22;
+ UINT32 InterTarget : 10;
- UINT32 CycleBit:1;
- UINT32 TC:1;
- UINT32 RsvdZ2:2;
- UINT32 CH:1;
- UINT32 IOC:1;
- UINT32 RsvdZ3:4;
- UINT32 Type:6;
- UINT32 RsvdZ4:16;
+ UINT32 CycleBit : 1;
+ UINT32 TC : 1;
+ UINT32 RsvdZ2 : 2;
+ UINT32 CH : 1;
+ UINT32 IOC : 1;
+ UINT32 RsvdZ3 : 4;
+ UINT32 Type : 6;
+ UINT32 RsvdZ4 : 16;
} LINK_TRB;
//
// 6.2.2 Slot Context
//
typedef struct _SLOT_CONTEXT {
- UINT32 RouteString:20;
- UINT32 Speed:4;
- UINT32 RsvdZ1:1;
- UINT32 MTT:1;
- UINT32 Hub:1;
- UINT32 ContextEntries:5;
-
- UINT32 MaxExitLatency:16;
- UINT32 RootHubPortNum:8;
- UINT32 PortNum:8;
-
- UINT32 TTHubSlotId:8;
- UINT32 TTPortNum:8;
- UINT32 TTT:2;
- UINT32 RsvdZ2:4;
- UINT32 InterTarget:10;
-
- UINT32 DeviceAddress:8;
- UINT32 RsvdZ3:19;
- UINT32 SlotState:5;
-
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
+ UINT32 RouteString : 20;
+ UINT32 Speed : 4;
+ UINT32 RsvdZ1 : 1;
+ UINT32 MTT : 1;
+ UINT32 Hub : 1;
+ UINT32 ContextEntries : 5;
+
+ UINT32 MaxExitLatency : 16;
+ UINT32 RootHubPortNum : 8;
+ UINT32 PortNum : 8;
+
+ UINT32 TTHubSlotId : 8;
+ UINT32 TTPortNum : 8;
+ UINT32 TTT : 2;
+ UINT32 RsvdZ2 : 4;
+ UINT32 InterTarget : 10;
+
+ UINT32 DeviceAddress : 8;
+ UINT32 RsvdZ3 : 19;
+ UINT32 SlotState : 5;
+
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
} SLOT_CONTEXT;
typedef struct _SLOT_CONTEXT_64 {
- UINT32 RouteString:20;
- UINT32 Speed:4;
- UINT32 RsvdZ1:1;
- UINT32 MTT:1;
- UINT32 Hub:1;
- UINT32 ContextEntries:5;
-
- UINT32 MaxExitLatency:16;
- UINT32 RootHubPortNum:8;
- UINT32 PortNum:8;
-
- UINT32 TTHubSlotId:8;
- UINT32 TTPortNum:8;
- UINT32 TTT:2;
- UINT32 RsvdZ2:4;
- UINT32 InterTarget:10;
-
- UINT32 DeviceAddress:8;
- UINT32 RsvdZ3:19;
- UINT32 SlotState:5;
-
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
-
- UINT32 RsvdZ8;
- UINT32 RsvdZ9;
- UINT32 RsvdZ10;
- UINT32 RsvdZ11;
-
- UINT32 RsvdZ12;
- UINT32 RsvdZ13;
- UINT32 RsvdZ14;
- UINT32 RsvdZ15;
-
+ UINT32 RouteString : 20;
+ UINT32 Speed : 4;
+ UINT32 RsvdZ1 : 1;
+ UINT32 MTT : 1;
+ UINT32 Hub : 1;
+ UINT32 ContextEntries : 5;
+
+ UINT32 MaxExitLatency : 16;
+ UINT32 RootHubPortNum : 8;
+ UINT32 PortNum : 8;
+
+ UINT32 TTHubSlotId : 8;
+ UINT32 TTPortNum : 8;
+ UINT32 TTT : 2;
+ UINT32 RsvdZ2 : 4;
+ UINT32 InterTarget : 10;
+
+ UINT32 DeviceAddress : 8;
+ UINT32 RsvdZ3 : 19;
+ UINT32 SlotState : 5;
+
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
+
+ UINT32 RsvdZ8;
+ UINT32 RsvdZ9;
+ UINT32 RsvdZ10;
+ UINT32 RsvdZ11;
+
+ UINT32 RsvdZ12;
+ UINT32 RsvdZ13;
+ UINT32 RsvdZ14;
+ UINT32 RsvdZ15;
} SLOT_CONTEXT_64;
-
//
// 6.2.3 Endpoint Context
//
typedef struct _ENDPOINT_CONTEXT {
- UINT32 EPState:3;
- UINT32 RsvdZ1:5;
- UINT32 Mult:2;
- UINT32 MaxPStreams:5;
- UINT32 LSA:1;
- UINT32 Interval:8;
- UINT32 RsvdZ2:8;
-
- UINT32 RsvdZ3:1;
- UINT32 CErr:2;
- UINT32 EPType:3;
- UINT32 RsvdZ4:1;
- UINT32 HID:1;
- UINT32 MaxBurstSize:8;
- UINT32 MaxPacketSize:16;
-
- UINT32 PtrLo;
-
- UINT32 PtrHi;
-
- UINT32 AverageTRBLength:16;
- UINT32 MaxESITPayload:16;
-
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
+ UINT32 EPState : 3;
+ UINT32 RsvdZ1 : 5;
+ UINT32 Mult : 2;
+ UINT32 MaxPStreams : 5;
+ UINT32 LSA : 1;
+ UINT32 Interval : 8;
+ UINT32 RsvdZ2 : 8;
+
+ UINT32 RsvdZ3 : 1;
+ UINT32 CErr : 2;
+ UINT32 EPType : 3;
+ UINT32 RsvdZ4 : 1;
+ UINT32 HID : 1;
+ UINT32 MaxBurstSize : 8;
+ UINT32 MaxPacketSize : 16;
+
+ UINT32 PtrLo;
+
+ UINT32 PtrHi;
+
+ UINT32 AverageTRBLength : 16;
+ UINT32 MaxESITPayload : 16;
+
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
} ENDPOINT_CONTEXT;
typedef struct _ENDPOINT_CONTEXT_64 {
- UINT32 EPState:3;
- UINT32 RsvdZ1:5;
- UINT32 Mult:2;
- UINT32 MaxPStreams:5;
- UINT32 LSA:1;
- UINT32 Interval:8;
- UINT32 RsvdZ2:8;
-
- UINT32 RsvdZ3:1;
- UINT32 CErr:2;
- UINT32 EPType:3;
- UINT32 RsvdZ4:1;
- UINT32 HID:1;
- UINT32 MaxBurstSize:8;
- UINT32 MaxPacketSize:16;
-
- UINT32 PtrLo;
-
- UINT32 PtrHi;
-
- UINT32 AverageTRBLength:16;
- UINT32 MaxESITPayload:16;
-
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
-
- UINT32 RsvdZ8;
- UINT32 RsvdZ9;
- UINT32 RsvdZ10;
- UINT32 RsvdZ11;
-
- UINT32 RsvdZ12;
- UINT32 RsvdZ13;
- UINT32 RsvdZ14;
- UINT32 RsvdZ15;
-
+ UINT32 EPState : 3;
+ UINT32 RsvdZ1 : 5;
+ UINT32 Mult : 2;
+ UINT32 MaxPStreams : 5;
+ UINT32 LSA : 1;
+ UINT32 Interval : 8;
+ UINT32 RsvdZ2 : 8;
+
+ UINT32 RsvdZ3 : 1;
+ UINT32 CErr : 2;
+ UINT32 EPType : 3;
+ UINT32 RsvdZ4 : 1;
+ UINT32 HID : 1;
+ UINT32 MaxBurstSize : 8;
+ UINT32 MaxPacketSize : 16;
+
+ UINT32 PtrLo;
+
+ UINT32 PtrHi;
+
+ UINT32 AverageTRBLength : 16;
+ UINT32 MaxESITPayload : 16;
+
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
+
+ UINT32 RsvdZ8;
+ UINT32 RsvdZ9;
+ UINT32 RsvdZ10;
+ UINT32 RsvdZ11;
+
+ UINT32 RsvdZ12;
+ UINT32 RsvdZ13;
+ UINT32 RsvdZ14;
+ UINT32 RsvdZ15;
} ENDPOINT_CONTEXT_64;
-
//
// 6.2.5.1 Input Control Context
//
typedef struct _INPUT_CONTRL_CONTEXT {
- UINT32 Dword1;
- UINT32 Dword2;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
- UINT32 RsvdZ3;
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
+ UINT32 Dword1;
+ UINT32 Dword2;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+ UINT32 RsvdZ3;
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
} INPUT_CONTRL_CONTEXT;
typedef struct _INPUT_CONTRL_CONTEXT_64 {
- UINT32 Dword1;
- UINT32 Dword2;
- UINT32 RsvdZ1;
- UINT32 RsvdZ2;
- UINT32 RsvdZ3;
- UINT32 RsvdZ4;
- UINT32 RsvdZ5;
- UINT32 RsvdZ6;
- UINT32 RsvdZ7;
- UINT32 RsvdZ8;
- UINT32 RsvdZ9;
- UINT32 RsvdZ10;
- UINT32 RsvdZ11;
- UINT32 RsvdZ12;
- UINT32 RsvdZ13;
- UINT32 RsvdZ14;
+ UINT32 Dword1;
+ UINT32 Dword2;
+ UINT32 RsvdZ1;
+ UINT32 RsvdZ2;
+ UINT32 RsvdZ3;
+ UINT32 RsvdZ4;
+ UINT32 RsvdZ5;
+ UINT32 RsvdZ6;
+ UINT32 RsvdZ7;
+ UINT32 RsvdZ8;
+ UINT32 RsvdZ9;
+ UINT32 RsvdZ10;
+ UINT32 RsvdZ11;
+ UINT32 RsvdZ12;
+ UINT32 RsvdZ13;
+ UINT32 RsvdZ14;
} INPUT_CONTRL_CONTEXT_64;
//
// 6.2.1 Device Context
//
typedef struct _DEVICE_CONTEXT {
- SLOT_CONTEXT Slot;
- ENDPOINT_CONTEXT EP[31];
+ SLOT_CONTEXT Slot;
+ ENDPOINT_CONTEXT EP[31];
} DEVICE_CONTEXT;
typedef struct _DEVICE_CONTEXT_64 {
- SLOT_CONTEXT_64 Slot;
- ENDPOINT_CONTEXT_64 EP[31];
+ SLOT_CONTEXT_64 Slot;
+ ENDPOINT_CONTEXT_64 EP[31];
} DEVICE_CONTEXT_64;
//
@@ -753,12 +749,11 @@ typedef struct _INPUT_CONTEXT { } INPUT_CONTEXT;
typedef struct _INPUT_CONTEXT_64 {
- INPUT_CONTRL_CONTEXT_64 InputControlContext;
- SLOT_CONTEXT_64 Slot;
- ENDPOINT_CONTEXT_64 EP[31];
+ INPUT_CONTRL_CONTEXT_64 InputControlContext;
+ SLOT_CONTEXT_64 Slot;
+ ENDPOINT_CONTEXT_64 EP[31];
} INPUT_CONTEXT_64;
-
/**
Initialize the XHCI host controller for schedule.
@@ -767,7 +762,7 @@ typedef struct _INPUT_CONTEXT_64 { **/
VOID
XhcInitSched (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -778,7 +773,7 @@ XhcInitSched ( **/
VOID
XhcFreeSched (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -792,8 +787,8 @@ XhcFreeSched ( **/
EFI_STATUS
RingIntTransferDoorBell (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
/**
@@ -811,10 +806,10 @@ RingIntTransferDoorBell ( **/
EFI_STATUS
XhcExecTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN BOOLEAN CmdTransfer,
- IN URB *Urb,
- IN UINTN Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN BOOLEAN CmdTransfer,
+ IN URB *Urb,
+ IN UINTN Timeout
);
/**
@@ -831,9 +826,9 @@ XhcExecTransfer ( **/
EFI_STATUS
XhciDelAsyncIntTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpNum
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpNum
);
/**
@@ -844,7 +839,7 @@ XhciDelAsyncIntTransfer ( **/
VOID
XhciDelAllAsyncIntTransfers (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -865,14 +860,14 @@ XhciDelAllAsyncIntTransfers ( **/
URB *
XhciInsertAsyncIntTransfer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
);
/**
@@ -883,7 +878,7 @@ XhciInsertAsyncIntTransfer ( **/
VOID
XhcSetBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -894,7 +889,7 @@ XhcSetBiosOwnership ( **/
VOID
XhcClearBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
);
/**
@@ -924,8 +919,8 @@ XhcRouteStringToSlotId ( **/
UINT8
XhcEndpointToDci (
- IN UINT8 EpAddr,
- IN UINT8 Direction
+ IN UINT8 EpAddr,
+ IN UINT8 Direction
);
/**
@@ -941,9 +936,9 @@ XhcEndpointToDci ( EFI_STATUS
EFIAPI
XhcRingDoorBell (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
);
/**
@@ -956,8 +951,8 @@ XhcRingDoorBell ( VOID
EFIAPI
XhcMonitorAsyncRequests (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
);
/**
@@ -975,10 +970,10 @@ XhcMonitorAsyncRequests ( EFI_STATUS
EFIAPI
XhcPollPortStatusChange (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT8 Port,
- IN EFI_USB_PORT_STATUS *PortState
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT8 Port,
+ IN EFI_USB_PORT_STATUS *PortState
);
/**
@@ -995,14 +990,13 @@ XhcPollPortStatusChange ( **/
EFI_STATUS
XhcConfigHubContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
);
-
/**
Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
@@ -1017,14 +1011,13 @@ XhcConfigHubContext ( **/
EFI_STATUS
XhcConfigHubContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
);
-
/**
Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
@@ -1039,13 +1032,12 @@ XhcConfigHubContext64 ( EFI_STATUS
EFIAPI
XhcSetConfigCmd (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
);
-
/**
Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
@@ -1060,10 +1052,10 @@ XhcSetConfigCmd ( EFI_STATUS
EFIAPI
XhcSetConfigCmd64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
);
/**
@@ -1081,11 +1073,11 @@ XhcSetConfigCmd64 ( EFI_STATUS
EFIAPI
XhcSetInterface (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
- IN EFI_USB_DEVICE_REQUEST *Request
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
+ IN EFI_USB_DEVICE_REQUEST *Request
);
/**
@@ -1103,11 +1095,11 @@ XhcSetInterface ( EFI_STATUS
EFIAPI
XhcSetInterface64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
- IN EFI_USB_DEVICE_REQUEST *Request
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
+ IN EFI_USB_DEVICE_REQUEST *Request
);
/**
@@ -1141,11 +1133,11 @@ XhcBusDevAddrToSlotId ( EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
);
/**
@@ -1163,11 +1155,11 @@ XhcInitializeDeviceSlot ( EFI_STATUS
EFIAPI
XhcInitializeDeviceSlot64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
);
/**
@@ -1183,12 +1175,11 @@ XhcInitializeDeviceSlot64 ( EFI_STATUS
EFIAPI
XhcEvaluateContext (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
);
-
/**
Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
@@ -1202,12 +1193,11 @@ XhcEvaluateContext ( EFI_STATUS
EFIAPI
XhcEvaluateContext64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
);
-
/**
Disable the specified device slot.
@@ -1220,11 +1210,10 @@ XhcEvaluateContext64 ( EFI_STATUS
EFIAPI
XhcDisableSlotCmd (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId
);
-
/**
Disable the specified device slot.
@@ -1237,11 +1226,10 @@ XhcDisableSlotCmd ( EFI_STATUS
EFIAPI
XhcDisableSlotCmd64 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId
);
-
/**
Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
@@ -1254,8 +1242,8 @@ XhcDisableSlotCmd64 ( EFI_STATUS
EFIAPI
XhcSyncTrsRing (
- IN USB_XHCI_INSTANCE *Xhc,
- TRANSFER_RING *TrsRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ TRANSFER_RING *TrsRing
);
/**
@@ -1270,8 +1258,8 @@ XhcSyncTrsRing ( EFI_STATUS
EFIAPI
XhcSyncEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- EVENT_RING *EvtRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ EVENT_RING *EvtRing
);
/**
@@ -1288,9 +1276,9 @@ XhcSyncEventRing ( EFI_STATUS
EFIAPI
XhcCheckNewEvent (
- IN USB_XHCI_INSTANCE *Xhc,
- IN EVENT_RING *EvtRing,
- OUT TRB_TEMPLATE **NewEvtTrb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN EVENT_RING *EvtRing,
+ OUT TRB_TEMPLATE **NewEvtTrb
);
/**
@@ -1303,9 +1291,9 @@ XhcCheckNewEvent ( **/
VOID
CreateTransferRing (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINTN TrbNum,
- OUT TRANSFER_RING *TransferRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINTN TrbNum,
+ OUT TRANSFER_RING *TransferRing
);
/**
@@ -1317,8 +1305,8 @@ CreateTransferRing ( **/
VOID
CreateEventRing (
- IN USB_XHCI_INSTANCE *Xhc,
- OUT EVENT_RING *EventRing
+ IN USB_XHCI_INSTANCE *Xhc,
+ OUT EVENT_RING *EventRing
);
/**
@@ -1338,8 +1326,8 @@ CreateEventRing ( EFI_STATUS
EFIAPI
XhcRecoverHaltedEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
/**
@@ -1358,8 +1346,8 @@ XhcRecoverHaltedEndpoint ( EFI_STATUS
EFIAPI
XhcDequeueTrbFromEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
/**
@@ -1377,10 +1365,10 @@ XhcDequeueTrbFromEndpoint ( EFI_STATUS
EFIAPI
XhcStopEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *PendingUrb OPTIONAL
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *PendingUrb OPTIONAL
);
/**
@@ -1397,9 +1385,9 @@ XhcStopEndpoint ( EFI_STATUS
EFIAPI
XhcResetEndpoint (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
);
/**
@@ -1418,10 +1406,10 @@ XhcResetEndpoint ( EFI_STATUS
EFIAPI
XhcSetTrDequeuePointer (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *Urb
);
/**
@@ -1442,19 +1430,19 @@ XhcSetTrDequeuePointer ( @return Created URB or NULL
**/
-URB*
+URB *
XhcCreateUrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 DevAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
);
/**
@@ -1466,8 +1454,8 @@ XhcCreateUrb ( **/
VOID
XhcFreeUrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
/**
@@ -1481,8 +1469,8 @@ XhcFreeUrb ( **/
EFI_STATUS
XhcCreateTransferTrb (
- IN USB_XHCI_INSTANCE *Xhc,
- IN URB *Urb
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN URB *Urb
);
#endif
|