diff options
Diffstat (limited to 'MdeModulePkg/Bus/Pci/EhciPei')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciPei/DmaMem.c | 89 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.c | 592 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.h | 116 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h | 127 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciPei/EhciSched.c | 142 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciPei/EhciSched.h | 18 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.c | 297 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.h | 300 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.c | 247 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.h | 31 |
10 files changed, 978 insertions, 981 deletions
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/DmaMem.c b/MdeModulePkg/Bus/Pci/EhciPei/DmaMem.c index 63870a1..320fb30 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/DmaMem.c +++ b/MdeModulePkg/Bus/Pci/EhciPei/DmaMem.c @@ -39,8 +39,8 @@ IoMmuMap ( OUT VOID **Mapping
)
{
- EFI_STATUS Status;
- UINT64 Attribute;
+ EFI_STATUS Status;
+ UINT64 Attribute;
if (IoMmu != NULL) {
Status = IoMmu->Map (
@@ -54,23 +54,25 @@ IoMmuMap ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
+
switch (Operation) {
- case EdkiiIoMmuOperationBusMasterRead:
- case EdkiiIoMmuOperationBusMasterRead64:
- Attribute = EDKII_IOMMU_ACCESS_READ;
- break;
- case EdkiiIoMmuOperationBusMasterWrite:
- case EdkiiIoMmuOperationBusMasterWrite64:
- Attribute = EDKII_IOMMU_ACCESS_WRITE;
- break;
- case EdkiiIoMmuOperationBusMasterCommonBuffer:
- case EdkiiIoMmuOperationBusMasterCommonBuffer64:
- Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
- break;
- default:
- ASSERT(FALSE);
- return EFI_INVALID_PARAMETER;
+ case EdkiiIoMmuOperationBusMasterRead:
+ case EdkiiIoMmuOperationBusMasterRead64:
+ Attribute = EDKII_IOMMU_ACCESS_READ;
+ break;
+ case EdkiiIoMmuOperationBusMasterWrite:
+ case EdkiiIoMmuOperationBusMasterWrite64:
+ Attribute = EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ case EdkiiIoMmuOperationBusMasterCommonBuffer:
+ case EdkiiIoMmuOperationBusMasterCommonBuffer64:
+ Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ default:
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
}
+
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -82,10 +84,11 @@ IoMmuMap ( return Status;
}
} else {
- *DeviceAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;
- *Mapping = NULL;
- Status = EFI_SUCCESS;
+ *DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
+ *Mapping = NULL;
+ Status = EFI_SUCCESS;
}
+
return Status;
}
@@ -98,8 +101,8 @@ IoMmuMap ( **/
VOID
IoMmuUnmap (
- IN EDKII_IOMMU_PPI *IoMmu,
- IN VOID *Mapping
+ IN EDKII_IOMMU_PPI *IoMmu,
+ IN VOID *Mapping
)
{
if (IoMmu != NULL) {
@@ -140,9 +143,9 @@ IoMmuAllocateBuffer ( UINTN NumberOfBytes;
EFI_PHYSICAL_ADDRESS HostPhyAddress;
- *HostAddress = NULL;
+ *HostAddress = NULL;
*DeviceAddress = 0;
- *Mapping = NULL;
+ *Mapping = NULL;
if (IoMmu != NULL) {
Status = IoMmu->AllocateBuffer (
@@ -157,19 +160,20 @@ IoMmuAllocateBuffer ( }
NumberOfBytes = EFI_PAGES_TO_SIZE (Pages);
- Status = IoMmu->Map (
- IoMmu,
- EdkiiIoMmuOperationBusMasterCommonBuffer,
- *HostAddress,
- &NumberOfBytes,
- DeviceAddress,
- Mapping
- );
+ Status = IoMmu->Map (
+ IoMmu,
+ EdkiiIoMmuOperationBusMasterCommonBuffer,
+ *HostAddress,
+ &NumberOfBytes,
+ DeviceAddress,
+ Mapping
+ );
if (EFI_ERROR (Status)) {
IoMmu->FreeBuffer (IoMmu, Pages, *HostAddress);
*HostAddress = NULL;
return EFI_OUT_OF_RESOURCES;
}
+
Status = IoMmu->SetAttribute (
IoMmu,
*Mapping,
@@ -178,7 +182,7 @@ IoMmuAllocateBuffer ( if (EFI_ERROR (Status)) {
IoMmu->Unmap (IoMmu, *Mapping);
IoMmu->FreeBuffer (IoMmu, Pages, *HostAddress);
- *Mapping = NULL;
+ *Mapping = NULL;
*HostAddress = NULL;
return Status;
}
@@ -191,10 +195,12 @@ IoMmuAllocateBuffer ( if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- *HostAddress = (VOID *) (UINTN) HostPhyAddress;
+
+ *HostAddress = (VOID *)(UINTN)HostPhyAddress;
*DeviceAddress = HostPhyAddress;
- *Mapping = NULL;
+ *Mapping = NULL;
}
+
return Status;
}
@@ -209,10 +215,10 @@ IoMmuAllocateBuffer ( **/
VOID
IoMmuFreeBuffer (
- IN EDKII_IOMMU_PPI *IoMmu,
- IN UINTN Pages,
- IN VOID *HostAddress,
- IN VOID *Mapping
+ IN EDKII_IOMMU_PPI *IoMmu,
+ IN UINTN Pages,
+ IN VOID *HostAddress,
+ IN VOID *Mapping
)
{
if (IoMmu != NULL) {
@@ -230,14 +236,13 @@ IoMmuFreeBuffer ( **/
VOID
IoMmuInit (
- OUT EDKII_IOMMU_PPI **IoMmu
+ OUT EDKII_IOMMU_PPI **IoMmu
)
{
PeiServicesLocatePpi (
&gEdkiiIoMmuPpiGuid,
0,
NULL,
- (VOID **) IoMmu
+ (VOID **)IoMmu
);
}
-
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.c b/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.c index cd1f879..37dd901 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.c +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.c @@ -15,19 +15,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // to the UEFI protocol's port state (change).
//
USB_PORT_STATE_MAP mUsbPortStateMap[] = {
- {PORTSC_CONN, USB_PORT_STAT_CONNECTION},
- {PORTSC_ENABLED, USB_PORT_STAT_ENABLE},
- {PORTSC_SUSPEND, USB_PORT_STAT_SUSPEND},
- {PORTSC_OVERCUR, USB_PORT_STAT_OVERCURRENT},
- {PORTSC_RESET, USB_PORT_STAT_RESET},
- {PORTSC_POWER, USB_PORT_STAT_POWER},
- {PORTSC_OWNER, USB_PORT_STAT_OWNER}
+ { PORTSC_CONN, USB_PORT_STAT_CONNECTION },
+ { PORTSC_ENABLED, USB_PORT_STAT_ENABLE },
+ { PORTSC_SUSPEND, USB_PORT_STAT_SUSPEND },
+ { PORTSC_OVERCUR, USB_PORT_STAT_OVERCURRENT },
+ { PORTSC_RESET, USB_PORT_STAT_RESET },
+ { PORTSC_POWER, USB_PORT_STAT_POWER },
+ { PORTSC_OWNER, USB_PORT_STAT_OWNER }
};
USB_PORT_STATE_MAP mUsbPortChangeMap[] = {
- {PORTSC_CONN_CHANGE, USB_PORT_STAT_C_CONNECTION},
- {PORTSC_ENABLE_CHANGE, USB_PORT_STAT_C_ENABLE},
- {PORTSC_OVERCUR_CHANGE, USB_PORT_STAT_C_OVERCURRENT}
+ { PORTSC_CONN_CHANGE, USB_PORT_STAT_C_CONNECTION },
+ { PORTSC_ENABLE_CHANGE, USB_PORT_STAT_C_ENABLE },
+ { PORTSC_OVERCUR_CHANGE, USB_PORT_STAT_C_OVERCURRENT }
};
/**
@@ -41,11 +41,11 @@ USB_PORT_STATE_MAP mUsbPortChangeMap[] = { **/
UINT32
EhcReadOpReg (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
+ UINT32 Data;
ASSERT (Ehc->CapLen != 0);
@@ -64,16 +64,14 @@ EhcReadOpReg ( **/
VOID
EhcWriteOpReg (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
-
ASSERT (Ehc->CapLen != 0);
- MmioWrite32(Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data);
-
+ MmioWrite32 (Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data);
}
/**
@@ -86,12 +84,12 @@ EhcWriteOpReg ( **/
VOID
EhcSetOpRegBit (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = EhcReadOpReg (Ehc, Offset);
Data |= Bit;
@@ -108,12 +106,12 @@ EhcSetOpRegBit ( **/
VOID
EhcClearOpRegBit (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = EhcReadOpReg (Ehc, Offset);
Data &= ~Bit;
@@ -136,14 +134,14 @@ EhcClearOpRegBit ( **/
EFI_STATUS
EhcWaitOpRegBit (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Bit,
- IN BOOLEAN WaitToSet,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Bit,
+ IN BOOLEAN WaitToSet,
+ IN UINT32 Timeout
)
{
- UINT32 Index;
+ UINT32 Index;
for (Index = 0; Index < Timeout / EHC_SYNC_POLL_INTERVAL + 1; Index++) {
if (EHC_REG_BIT_IS_SET (Ehc, Offset, Bit) == WaitToSet) {
@@ -167,13 +165,13 @@ EhcWaitOpRegBit ( **/
UINT32
EhcReadCapRegister (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
+ UINT32 Data;
- Data = MmioRead32(Ehc->UsbHostControllerBaseAddress + Offset);
+ Data = MmioRead32 (Ehc->UsbHostControllerBaseAddress + Offset);
return Data;
}
@@ -191,12 +189,12 @@ EhcReadCapRegister ( **/
EFI_STATUS
EhcSetAndWaitDoorBell (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
- UINT32 Data;
+ EFI_STATUS Status;
+ UINT32 Data;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_IAAD);
@@ -224,7 +222,7 @@ EhcSetAndWaitDoorBell ( **/
VOID
EhcAckAllInterrupt (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, USBSTS_INTACK_MASK);
@@ -243,11 +241,11 @@ EhcAckAllInterrupt ( **/
EFI_STATUS
EhcEnablePeriodSchd (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);
@@ -267,11 +265,11 @@ EhcEnablePeriodSchd ( **/
EFI_STATUS
EhcEnableAsyncSchd (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);
@@ -290,7 +288,7 @@ EhcEnableAsyncSchd ( **/
BOOLEAN
EhcIsHalt (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT);
@@ -307,7 +305,7 @@ EhcIsHalt ( **/
BOOLEAN
EhcIsSysError (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
return EHC_REG_BIT_IS_SET (Ehc, EHC_USBSTS_OFFSET, USBSTS_SYS_ERROR);
@@ -325,11 +323,11 @@ EhcIsSysError ( **/
EFI_STATUS
EhcResetHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Host can only be reset when it is halt. If not so, halt it
@@ -359,11 +357,11 @@ EhcResetHC ( **/
EFI_STATUS
EhcHaltHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, TRUE, Timeout);
@@ -382,11 +380,11 @@ EhcHaltHC ( **/
EFI_STATUS
EhcRunHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_HALT, FALSE, Timeout);
@@ -401,12 +399,12 @@ EhcRunHC ( **/
VOID
EhcPowerOnAllPorts (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
- UINT8 PortNumber;
- UINT8 Index;
- UINT32 RegVal;
+ UINT8 PortNumber;
+ UINT8 Index;
+ UINT32 RegVal;
PortNumber = (UINT8)(Ehc->HcStructParams & HCSP_NPORTS);
for (Index = 0; Index < PortNumber; Index++) {
@@ -414,7 +412,7 @@ EhcPowerOnAllPorts ( // Do not clear port status bits on initialization. Otherwise devices will
// not enumerate properly at startup.
//
- RegVal = EhcReadOpReg(Ehc, EHC_PORT_STAT_OFFSET + 4 * Index);
+ RegVal = EhcReadOpReg (Ehc, EHC_PORT_STAT_OFFSET + 4 * Index);
RegVal &= ~PORTSC_CHANGE_MASK;
RegVal |= PORTSC_POWER;
EhcWriteOpReg (Ehc, EHC_PORT_STAT_OFFSET + 4 * Index, RegVal);
@@ -438,12 +436,12 @@ EhcPowerOnAllPorts ( **/
EFI_STATUS
EhcInitHC (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS TempPtr;
- UINTN PageNumber;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS TempPtr;
+ UINTN PageNumber;
ASSERT (EhcIsHalt (Ehc));
@@ -454,13 +452,14 @@ EhcInitHC ( if (Ehc->PeriodFrame != NULL) {
EhcFreeSched (Ehc);
}
- PageNumber = sizeof(PEI_URB)/PAGESIZE +1;
- Status = PeiServicesAllocatePages (
- EfiBootServicesCode,
- PageNumber,
- &TempPtr
- );
- Ehc->Urb = (PEI_URB *) ((UINTN) TempPtr);
+
+ PageNumber = sizeof (PEI_URB)/PAGESIZE +1;
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesCode,
+ PageNumber,
+ &TempPtr
+ );
+ Ehc->Urb = (PEI_URB *)((UINTN)TempPtr);
if (Ehc->Urb == NULL) {
return Status;
}
@@ -473,6 +472,7 @@ EhcInitHC ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// 1. Program the CTRLDSSEGMENT register with the high 32 bit addr
//
@@ -563,15 +563,16 @@ EhcBulkTransfer ( OUT UINT32 *TransferResult
)
{
- PEI_USB2_HC_DEV *Ehc;
- PEI_URB *Urb;
- EFI_STATUS Status;
+ PEI_USB2_HC_DEV *Ehc;
+ PEI_URB *Urb;
+ EFI_STATUS Status;
//
// Validate the parameters
//
if ((DataLength == NULL) || (*DataLength == 0) ||
- (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {
+ (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -581,11 +582,12 @@ EhcBulkTransfer ( if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
- ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512))) {
+ ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)))
+ {
return EFI_INVALID_PARAMETER;
}
- Ehc =PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(This);
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
*TransferResult = EFI_USB_ERR_SYSTEM;
Status = EFI_DEVICE_ERROR;
@@ -656,13 +658,13 @@ ON_EXIT: EFI_STATUS
EFIAPI
EhcGetRootHubPortNumber (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- OUT UINT8 *PortNumber
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ OUT UINT8 *PortNumber
)
{
+ PEI_USB2_HC_DEV *EhcDev;
- PEI_USB2_HC_DEV *EhcDev;
EhcDev = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
if (PortNumber == NULL) {
@@ -671,7 +673,6 @@ EhcGetRootHubPortNumber ( *PortNumber = (UINT8)(EhcDev->HcStructParams & HCSP_NPORTS);
return EFI_SUCCESS;
-
}
/**
@@ -692,20 +693,20 @@ EhcGetRootHubPortNumber ( EFI_STATUS
EFIAPI
EhcClearRootHubPortFeature (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- IN EFI_USB_PORT_FEATURE PortFeature
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ IN EFI_USB_PORT_FEATURE PortFeature
)
{
- PEI_USB2_HC_DEV *Ehc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- EFI_STATUS Status;
+ PEI_USB2_HC_DEV *Ehc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ EFI_STATUS Status;
- Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
- Status = EFI_SUCCESS;
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);
@@ -714,82 +715,82 @@ EhcClearRootHubPortFeature ( goto ON_EXIT;
}
- Offset = EHC_PORT_STAT_OFFSET + (4 * PortNumber);
- State = EhcReadOpReg (Ehc, Offset);
+ Offset = EHC_PORT_STAT_OFFSET + (4 * PortNumber);
+ State = EhcReadOpReg (Ehc, Offset);
State &= ~PORTSC_CHANGE_MASK;
switch (PortFeature) {
- case EfiUsbPortEnable:
- //
- // Clear PORT_ENABLE feature means disable port.
- //
- State &= ~PORTSC_ENABLED;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortEnable:
+ //
+ // Clear PORT_ENABLE feature means disable port.
+ //
+ State &= ~PORTSC_ENABLED;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortSuspend:
- //
- // A write of zero to this bit is ignored by the host
- // controller. The host controller will unconditionally
- // set this bit to a zero when:
- // 1. software sets the Forct Port Resume bit to a zero from a one.
- // 2. software sets the Port Reset bit to a one frome a zero.
- //
- State &= ~PORSTSC_RESUME;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortSuspend:
+ //
+ // A write of zero to this bit is ignored by the host
+ // controller. The host controller will unconditionally
+ // set this bit to a zero when:
+ // 1. software sets the Forct Port Resume bit to a zero from a one.
+ // 2. software sets the Port Reset bit to a one frome a zero.
+ //
+ State &= ~PORSTSC_RESUME;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortReset:
- //
- // Clear PORT_RESET means clear the reset signal.
- //
- State &= ~PORTSC_RESET;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortReset:
+ //
+ // Clear PORT_RESET means clear the reset signal.
+ //
+ State &= ~PORTSC_RESET;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortOwner:
- //
- // Clear port owner means this port owned by EHC
- //
- State &= ~PORTSC_OWNER;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortOwner:
+ //
+ // Clear port owner means this port owned by EHC
+ //
+ State &= ~PORTSC_OWNER;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortConnectChange:
- //
- // Clear connect status change
- //
- State |= PORTSC_CONN_CHANGE;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortConnectChange:
+ //
+ // Clear connect status change
+ //
+ State |= PORTSC_CONN_CHANGE;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortEnableChange:
- //
- // Clear enable status change
- //
- State |= PORTSC_ENABLE_CHANGE;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortEnableChange:
+ //
+ // Clear enable status change
+ //
+ State |= PORTSC_ENABLE_CHANGE;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortOverCurrentChange:
- //
- // Clear PortOverCurrent change
- //
- State |= PORTSC_OVERCUR_CHANGE;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortOverCurrentChange:
+ //
+ // Clear PortOverCurrent change
+ //
+ State |= PORTSC_OVERCUR_CHANGE;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortPower:
- case EfiUsbPortSuspendChange:
- case EfiUsbPortResetChange:
- //
- // Not supported or not related operation
- //
- break;
+ case EfiUsbPortPower:
+ case EfiUsbPortSuspendChange:
+ case EfiUsbPortResetChange:
+ //
+ // Not supported or not related operation
+ //
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
- break;
+ default:
+ Status = EFI_INVALID_PARAMETER;
+ break;
}
ON_EXIT:
@@ -812,20 +813,20 @@ ON_EXIT: EFI_STATUS
EFIAPI
EhcSetRootHubPortFeature (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- IN EFI_USB_PORT_FEATURE PortFeature
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ IN EFI_USB_PORT_FEATURE PortFeature
)
{
- PEI_USB2_HC_DEV *Ehc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- EFI_STATUS Status;
+ PEI_USB2_HC_DEV *Ehc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ EFI_STATUS Status;
- Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
- Status = EFI_SUCCESS;
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);
@@ -834,8 +835,8 @@ EhcSetRootHubPortFeature ( goto ON_EXIT;
}
- Offset = (UINT32) (EHC_PORT_STAT_OFFSET + (4 * PortNumber));
- State = EhcReadOpReg (Ehc, Offset);
+ Offset = (UINT32)(EHC_PORT_STAT_OFFSET + (4 * PortNumber));
+ State = EhcReadOpReg (Ehc, Offset);
//
// Mask off the port status change bits, these bits are
@@ -844,54 +845,54 @@ EhcSetRootHubPortFeature ( State &= ~PORTSC_CHANGE_MASK;
switch (PortFeature) {
- case EfiUsbPortEnable:
- //
- // Sofeware can't set this bit, Port can only be enable by
- // EHCI as a part of the reset and enable
- //
- State |= PORTSC_ENABLED;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortEnable:
+ //
+ // Sofeware can't set this bit, Port can only be enable by
+ // EHCI as a part of the reset and enable
+ //
+ State |= PORTSC_ENABLED;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortSuspend:
- State |= PORTSC_SUSPEND;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortSuspend:
+ State |= PORTSC_SUSPEND;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortReset:
- //
- // Make sure Host Controller not halt before reset it
- //
- if (EhcIsHalt (Ehc)) {
- Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);
+ case EfiUsbPortReset:
+ //
+ // Make sure Host Controller not halt before reset it
+ //
+ if (EhcIsHalt (Ehc)) {
+ Status = EhcRunHC (Ehc, EHC_GENERIC_TIMEOUT);
- if (EFI_ERROR (Status)) {
- break;
+ if (EFI_ERROR (Status)) {
+ break;
+ }
}
- }
- //
- // Set one to PortReset bit must also set zero to PortEnable bit
- //
- State |= PORTSC_RESET;
- State &= ~PORTSC_ENABLED;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ //
+ // Set one to PortReset bit must also set zero to PortEnable bit
+ //
+ State |= PORTSC_RESET;
+ State &= ~PORTSC_ENABLED;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- case EfiUsbPortPower:
- //
- // Not supported, ignore the operation
- //
- Status = EFI_SUCCESS;
- break;
+ case EfiUsbPortPower:
+ //
+ // Not supported, ignore the operation
+ //
+ Status = EFI_SUCCESS;
+ break;
- case EfiUsbPortOwner:
- State |= PORTSC_OWNER;
- EhcWriteOpReg (Ehc, Offset, State);
- break;
+ case EfiUsbPortOwner:
+ State |= PORTSC_OWNER;
+ EhcWriteOpReg (Ehc, Offset, State);
+ break;
- default:
- Status = EFI_INVALID_PARAMETER;
+ default:
+ Status = EFI_INVALID_PARAMETER;
}
ON_EXIT:
@@ -914,26 +915,26 @@ ON_EXIT: EFI_STATUS
EFIAPI
EhcGetRootHubPortStatus (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_USB2_HOST_CONTROLLER_PPI *This,
- IN UINT8 PortNumber,
- OUT EFI_USB_PORT_STATUS *PortStatus
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_USB2_HOST_CONTROLLER_PPI *This,
+ IN UINT8 PortNumber,
+ OUT EFI_USB_PORT_STATUS *PortStatus
)
{
- PEI_USB2_HC_DEV *Ehc;
- UINT32 Offset;
- UINT32 State;
- UINT32 TotalPort;
- UINTN Index;
- UINTN MapSize;
- EFI_STATUS Status;
+ PEI_USB2_HC_DEV *Ehc;
+ UINT32 Offset;
+ UINT32 State;
+ UINT32 TotalPort;
+ UINTN Index;
+ UINTN MapSize;
+ EFI_STATUS Status;
if (PortStatus == NULL) {
return EFI_INVALID_PARAMETER;
}
- Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(This);
- Status = EFI_SUCCESS;
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
+ Status = EFI_SUCCESS;
TotalPort = (Ehc->HcStructParams & HCSP_NPORTS);
@@ -942,11 +943,11 @@ EhcGetRootHubPortStatus ( goto ON_EXIT;
}
- Offset = (UINT32) (EHC_PORT_STAT_OFFSET + (4 * PortNumber));
- PortStatus->PortStatus = 0;
- PortStatus->PortChangeStatus = 0;
+ Offset = (UINT32)(EHC_PORT_STAT_OFFSET + (4 * PortNumber));
+ PortStatus->PortStatus = 0;
+ PortStatus->PortChangeStatus = 0;
- State = EhcReadOpReg (Ehc, Offset);
+ State = EhcReadOpReg (Ehc, Offset);
//
// Identify device speed. If in K state, it is low speed.
@@ -956,7 +957,6 @@ EhcGetRootHubPortStatus ( //
if (EHC_BIT_IS_SET (State, PORTSC_LINESTATE_K)) {
PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
-
} else if (EHC_BIT_IS_SET (State, PORTSC_ENABLED)) {
PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
}
@@ -968,7 +968,7 @@ EhcGetRootHubPortStatus ( for (Index = 0; Index < MapSize; Index++) {
if (EHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {
- PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
+ PortStatus->PortStatus = (UINT16)(PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
}
}
@@ -976,7 +976,7 @@ EhcGetRootHubPortStatus ( for (Index = 0; Index < MapSize; Index++) {
if (EHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {
- PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
+ PortStatus->PortChangeStatus = (UINT16)(PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
}
}
@@ -1027,10 +1027,10 @@ EhcControlTransfer ( OUT UINT32 *TransferResult
)
{
- PEI_USB2_HC_DEV *Ehc;
- PEI_URB *Urb;
- UINT8 Endpoint;
- EFI_STATUS Status;
+ PEI_USB2_HC_DEV *Ehc;
+ PEI_URB *Urb;
+ UINT8 Endpoint;
+ EFI_STATUS Status;
//
// Validate parameters
@@ -1041,33 +1041,37 @@ EhcControlTransfer ( if ((TransferDirection != EfiUsbDataIn) &&
(TransferDirection != EfiUsbDataOut) &&
- (TransferDirection != EfiUsbNoData)) {
+ (TransferDirection != EfiUsbNoData))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection == EfiUsbNoData) &&
- ((Data != NULL) || (*DataLength != 0))) {
+ ((Data != NULL) || (*DataLength != 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((TransferDirection != EfiUsbNoData) &&
- ((Data == NULL) || (*DataLength == 0))) {
+ ((Data == NULL) || (*DataLength == 0)))
+ {
return EFI_INVALID_PARAMETER;
}
if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&
- (MaximumPacketLength != 32) && (MaximumPacketLength != 64)) {
+ (MaximumPacketLength != 32) && (MaximumPacketLength != 64))
+ {
return EFI_INVALID_PARAMETER;
}
-
if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
- ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512))) {
+ ((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)))
+ {
return EFI_INVALID_PARAMETER;
}
- Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
+ Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS (This);
Status = EFI_DEVICE_ERROR;
*TransferResult = EFI_USB_ERR_SYSTEM;
@@ -1088,23 +1092,23 @@ EhcControlTransfer ( // endpoint is bidirectional. EhcCreateUrb expects this
// combination of Ep addr and its direction.
//
- Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
- Urb = EhcCreateUrb (
- Ehc,
- DeviceAddress,
- Endpoint,
- DeviceSpeed,
- 0,
- MaximumPacketLength,
- Translator,
- EHC_CTRL_TRANSFER,
- Request,
- Data,
- *DataLength,
- NULL,
- NULL,
- 1
- );
+ Endpoint = (UINT8)(0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
+ Urb = EhcCreateUrb (
+ Ehc,
+ DeviceAddress,
+ Endpoint,
+ DeviceSpeed,
+ 0,
+ MaximumPacketLength,
+ Translator,
+ EHC_CTRL_TRANSFER,
+ Request,
+ Data,
+ *DataLength,
+ NULL,
+ NULL,
+ 1
+ );
if (Urb == NULL) {
Status = EFI_OUT_OF_RESOURCES;
@@ -1152,7 +1156,7 @@ EhcEndOfPei ( IN VOID *Ppi
)
{
- PEI_USB2_HC_DEV *Ehc;
+ PEI_USB2_HC_DEV *Ehc;
Ehc = PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY (NotifyDescriptor);
@@ -1177,14 +1181,14 @@ EhcPeimEntry ( IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;
- EFI_STATUS Status;
- UINT8 Index;
- UINTN ControllerType;
- UINTN BaseAddress;
- UINTN MemPages;
- PEI_USB2_HC_DEV *EhcDev;
- EFI_PHYSICAL_ADDRESS TempPtr;
+ PEI_USB_CONTROLLER_PPI *ChipSetUsbControllerPpi;
+ EFI_STATUS Status;
+ UINT8 Index;
+ UINTN ControllerType;
+ UINTN BaseAddress;
+ UINTN MemPages;
+ PEI_USB2_HC_DEV *EhcDev;
+ EFI_PHYSICAL_ADDRESS TempPtr;
//
// Shadow this PEIM to run from memory
@@ -1197,7 +1201,7 @@ EhcPeimEntry ( &gPeiUsbControllerPpiGuid,
0,
NULL,
- (VOID **) &ChipSetUsbControllerPpi
+ (VOID **)&ChipSetUsbControllerPpi
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
@@ -1206,7 +1210,7 @@ EhcPeimEntry ( Index = 0;
while (TRUE) {
Status = ChipSetUsbControllerPpi->GetUsbController (
- (EFI_PEI_SERVICES **) PeiServices,
+ (EFI_PEI_SERVICES **)PeiServices,
ChipSetUsbControllerPpi,
Index,
&ControllerType,
@@ -1228,24 +1232,23 @@ EhcPeimEntry ( }
MemPages = sizeof (PEI_USB2_HC_DEV) / PAGESIZE + 1;
- Status = PeiServicesAllocatePages (
- EfiBootServicesCode,
- MemPages,
- &TempPtr
- );
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesCode,
+ MemPages,
+ &TempPtr
+ );
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- ZeroMem((VOID *)(UINTN)TempPtr, MemPages*PAGESIZE);
- EhcDev = (PEI_USB2_HC_DEV *) ((UINTN) TempPtr);
+ ZeroMem ((VOID *)(UINTN)TempPtr, MemPages*PAGESIZE);
+ EhcDev = (PEI_USB2_HC_DEV *)((UINTN)TempPtr);
EhcDev->Signature = USB2_HC_DEV_SIGNATURE;
IoMmuInit (&EhcDev->IoMmu);
- EhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress;
-
+ EhcDev->UsbHostControllerBaseAddress = (UINT32)BaseAddress;
EhcDev->HcStructParams = EhcReadCapRegister (EhcDev, EHC_HCSPARAMS_OFFSET);
EhcDev->HcCapParams = EhcReadCapRegister (EhcDev, EHC_HCCPARAMS_OFFSET);
@@ -1258,16 +1261,16 @@ EhcPeimEntry ( return Status;
}
- EhcDev->Usb2HostControllerPpi.ControlTransfer = EhcControlTransfer;
- EhcDev->Usb2HostControllerPpi.BulkTransfer = EhcBulkTransfer;
- EhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = EhcGetRootHubPortNumber;
- EhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = EhcGetRootHubPortStatus;
- EhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = EhcSetRootHubPortFeature;
- EhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = EhcClearRootHubPortFeature;
+ EhcDev->Usb2HostControllerPpi.ControlTransfer = EhcControlTransfer;
+ EhcDev->Usb2HostControllerPpi.BulkTransfer = EhcBulkTransfer;
+ EhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = EhcGetRootHubPortNumber;
+ EhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = EhcGetRootHubPortStatus;
+ EhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = EhcSetRootHubPortFeature;
+ EhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = EhcClearRootHubPortFeature;
EhcDev->PpiDescriptor.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
- EhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;
- EhcDev->PpiDescriptor.Ppi = &EhcDev->Usb2HostControllerPpi;
+ EhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;
+ EhcDev->PpiDescriptor.Ppi = &EhcDev->Usb2HostControllerPpi;
Status = PeiServicesInstallPpi (&EhcDev->PpiDescriptor);
if (EFI_ERROR (Status)) {
@@ -1275,8 +1278,8 @@ EhcPeimEntry ( continue;
}
- EhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
- EhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;
+ EhcDev->EndOfPeiNotifyList.Flags = (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
+ EhcDev->EndOfPeiNotifyList.Guid = &gEfiEndOfPeiSignalPpiGuid;
EhcDev->EndOfPeiNotifyList.Notify = EhcEndOfPei;
PeiServicesNotifyPpi (&EhcDev->EndOfPeiNotifyList);
@@ -1296,12 +1299,11 @@ EhcPeimEntry ( **/
EFI_STATUS
InitializeUsbHC (
- IN PEI_USB2_HC_DEV *EhcDev
+ IN PEI_USB2_HC_DEV *EhcDev
)
{
EFI_STATUS Status;
-
EhcResetHC (EhcDev, EHC_RESET_TIMEOUT);
Status = EhcInitHC (EhcDev);
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.h b/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.h index 8e5b641..c83886c 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.h +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.h @@ -28,46 +28,44 @@ SPDX-License-Identifier: BSD-2-Clause-Patent typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV;
-#define EFI_LIST_ENTRY LIST_ENTRY
+#define EFI_LIST_ENTRY LIST_ENTRY
#include "UsbHcMem.h"
#include "EhciReg.h"
#include "EhciUrb.h"
#include "EhciSched.h"
-#define EFI_USB_SPEED_FULL 0x0000
-#define EFI_USB_SPEED_LOW 0x0001
-#define EFI_USB_SPEED_HIGH 0x0002
+#define EFI_USB_SPEED_FULL 0x0000
+#define EFI_USB_SPEED_LOW 0x0001
+#define EFI_USB_SPEED_HIGH 0x0002
-#define PAGESIZE 4096
+#define PAGESIZE 4096
-#define EHC_1_MICROSECOND 1
-#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
-#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
+#define EHC_1_MICROSECOND 1
+#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
+#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
//
// EHCI register operation timeout, set by experience
//
-#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
-#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
-
+#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
+#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
//
// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
//
-#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
+#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
//
// Sync transfer polling interval, set by experience.
//
-#define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)
-
-#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
+#define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND)
+#define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
-#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
-#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
-#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
+#define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
+#define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
+#define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \
(EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))
@@ -75,18 +73,18 @@ typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV; #define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')
struct _PEI_USB2_HC_DEV {
- UINTN Signature;
- PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
- EDKII_IOMMU_PPI *IoMmu;
- EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
+ UINTN Signature;
+ PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
+ EDKII_IOMMU_PPI *IoMmu;
+ EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
//
// EndOfPei callback is used to stop the EHC DMA operation
// after exit PEI phase.
//
- EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
- UINT32 UsbHostControllerBaseAddress;
- PEI_URB *Urb;
- USBHC_MEM_POOL *MemPool;
+ EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
+ UINT32 UsbHostControllerBaseAddress;
+ PEI_URB *Urb;
+ USBHC_MEM_POOL *MemPool;
//
// Schedule data shared between asynchronous and periodic
@@ -97,36 +95,36 @@ struct _PEI_USB2_HC_DEV { // For control transfer, even the short read happens, try the
// status stage.
//
- PEI_EHC_QTD *ShortReadStop;
- EFI_EVENT PollTimer;
+ PEI_EHC_QTD *ShortReadStop;
+ EFI_EVENT PollTimer;
//
// Asynchronous(bulk and control) transfer schedule data:
// ReclaimHead is used as the head of the asynchronous transfer
// list. It acts as the reclamation header.
//
- PEI_EHC_QH *ReclaimHead;
+ PEI_EHC_QH *ReclaimHead;
//
// Periodic (interrupt) transfer schedule data:
//
- VOID *PeriodFrame; // Mapped as common buffer
- VOID *PeriodFrameMap;
+ VOID *PeriodFrame; // Mapped as common buffer
+ VOID *PeriodFrameMap;
- PEI_EHC_QH *PeriodOne;
- EFI_LIST_ENTRY AsyncIntTransfers;
+ PEI_EHC_QH *PeriodOne;
+ EFI_LIST_ENTRY AsyncIntTransfers;
//
// EHCI configuration data
//
- UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
- UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
- UINT32 CapLen; // Capability length
- UINT32 High32bitAddr;
+ UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
+ UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS
+ UINT32 CapLen; // Capability length
+ UINT32 High32bitAddr;
};
-#define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)
-#define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)
+#define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)
+#define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)
/**
@param EhcDev EHCI Device.
@@ -137,7 +135,7 @@ struct _PEI_USB2_HC_DEV { **/
EFI_STATUS
InitializeUsbHC (
- IN PEI_USB2_HC_DEV *EhcDev
+ IN PEI_USB2_HC_DEV *EhcDev
);
/**
@@ -154,9 +152,9 @@ InitializeUsbHC ( **/
USBHC_MEM_POOL *
UsbHcInitMemPool (
- IN PEI_USB2_HC_DEV *Ehc,
- IN BOOLEAN Check4G,
- IN UINT32 Which4G
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN BOOLEAN Check4G,
+ IN UINT32 Which4G
)
;
@@ -172,8 +170,8 @@ UsbHcInitMemPool ( **/
EFI_STATUS
UsbHcFreeMemPool (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool
)
;
@@ -190,9 +188,9 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
)
;
@@ -207,10 +205,10 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
;
@@ -253,8 +251,8 @@ IoMmuMap ( **/
VOID
IoMmuUnmap (
- IN EDKII_IOMMU_PPI *IoMmu,
- IN VOID *Mapping
+ IN EDKII_IOMMU_PPI *IoMmu,
+ IN VOID *Mapping
);
/**
@@ -296,10 +294,10 @@ IoMmuAllocateBuffer ( **/
VOID
IoMmuFreeBuffer (
- IN EDKII_IOMMU_PPI *IoMmu,
- IN UINTN Pages,
- IN VOID *HostAddress,
- IN VOID *Mapping
+ IN EDKII_IOMMU_PPI *IoMmu,
+ IN UINTN Pages,
+ IN VOID *HostAddress,
+ IN VOID *Mapping
);
/**
@@ -310,7 +308,7 @@ IoMmuFreeBuffer ( **/
VOID
IoMmuInit (
- OUT EDKII_IOMMU_PPI **IoMmu
+ OUT EDKII_IOMMU_PPI **IoMmu
);
#endif
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h b/MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h index 9811351..2a438f1 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h @@ -10,20 +10,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_EHCI_REG_H_
#define _EFI_EHCI_REG_H_
-
-
//
// Capability register offset
//
-#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
-#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
-#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
+#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
+#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
+#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
//
// Capability register bit definition
//
-#define HCSP_NPORTS 0x0F // Number of root hub port
-#define HCCP_64BIT 0x01 // 64-bit addressing capability
+#define HCSP_NPORTS 0x0F // Number of root hub port
+#define HCCP_64BIT 0x01 // 64-bit addressing capability
//
// Operational register offset
@@ -38,61 +36,61 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
-#define EHC_FRAME_LEN 1024
+#define EHC_FRAME_LEN 1024
//
// Register bit definition
//
-#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
-
-#define USBCMD_RUN 0x01 // Run/stop
-#define USBCMD_RESET 0x02 // Start the host controller reset
-#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
-#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
-#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
-
-#define USBSTS_IAA 0x20 // Interrupt on async advance
-#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
-#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
-#define USBSTS_HALT 0x1000 // Host controller halted
-#define USBSTS_SYS_ERROR 0x10 // Host system error
-#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
+#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
+
+#define USBCMD_RUN 0x01 // Run/stop
+#define USBCMD_RESET 0x02 // Start the host controller reset
+#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
+#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
+#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
+
+#define USBSTS_IAA 0x20 // Interrupt on async advance
+#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
+#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
+#define USBSTS_HALT 0x1000 // Host controller halted
+#define USBSTS_SYS_ERROR 0x10 // Host system error
+#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
// (write clean) bits in USBSTS register
-#define PORTSC_CONN 0x01 // Current Connect Status
-#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
-#define PORTSC_ENABLED 0x04 // Port Enable / Disable
-#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
-#define PORTSC_OVERCUR 0x10 // Over current Active
-#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
-#define PORSTSC_RESUME 0x40 // Force Port Resume
-#define PORTSC_SUSPEND 0x80 // Port Suspend State
-#define PORTSC_RESET 0x100 // Port Reset
-#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
-#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
-#define PORTSC_POWER 0x1000 // Port Power
-#define PORTSC_OWNER 0x2000 // Port Owner
-#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
+#define PORTSC_CONN 0x01 // Current Connect Status
+#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
+#define PORTSC_ENABLED 0x04 // Port Enable / Disable
+#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
+#define PORTSC_OVERCUR 0x10 // Over current Active
+#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
+#define PORSTSC_RESUME 0x40 // Force Port Resume
+#define PORTSC_SUSPEND 0x80 // Port Suspend State
+#define PORTSC_RESET 0x100 // Port Reset
+#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
+#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
+#define PORTSC_POWER 0x1000 // Port Power
+#define PORTSC_OWNER 0x2000 // Port Owner
+#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
// they are WC (write clean)
//
// PCI Configuration Registers
//
-#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
+#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
-#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
+#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define EHC_ADDR(High, QhHw32) \
((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
-#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
+#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
//
// Structure to map the hardware port states to the
// UEFI's port states.
//
typedef struct {
- UINT16 HwState;
- UINT16 UefiState;
+ UINT16 HwState;
+ UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
@@ -100,13 +98,12 @@ typedef struct { //
#pragma pack(1)
typedef struct {
- UINT8 Pi;
- UINT8 SubClassCode;
- UINT8 BaseCode;
+ UINT8 Pi;
+ UINT8 SubClassCode;
+ UINT8 BaseCode;
} USB_CLASSC;
#pragma pack()
-
/**
Read EHCI capability register.
@@ -118,8 +115,8 @@ typedef struct { **/
UINT32
EhcReadCapRegister (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
;
@@ -134,8 +131,8 @@ EhcReadCapRegister ( **/
UINT32
EhcReadOpReg (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
;
@@ -149,9 +146,9 @@ EhcReadOpReg ( **/
VOID
EhcWriteOpReg (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
;
@@ -163,7 +160,7 @@ EhcWriteOpReg ( **/
VOID
EhcClearLegacySupport (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -180,8 +177,8 @@ EhcClearLegacySupport ( **/
EFI_STATUS
EhcSetAndWaitDoorBell (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
;
@@ -194,7 +191,7 @@ EhcSetAndWaitDoorBell ( **/
VOID
EhcAckAllInterrupt (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -209,7 +206,7 @@ EhcAckAllInterrupt ( **/
BOOLEAN
EhcIsHalt (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -224,7 +221,7 @@ EhcIsHalt ( **/
BOOLEAN
EhcIsSysError (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -240,8 +237,8 @@ EhcIsSysError ( **/
EFI_STATUS
EhcResetHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
;
@@ -257,8 +254,8 @@ EhcResetHC ( **/
EFI_STATUS
EhcHaltHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
;
@@ -274,8 +271,8 @@ EhcHaltHC ( **/
EFI_STATUS
EhcRunHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
;
@@ -296,7 +293,7 @@ EhcRunHC ( **/
EFI_STATUS
EhcInitHC (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.c b/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.c index 311f501..db2406b 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.c +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.c @@ -22,13 +22,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
EhcCreateHelpQ (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
- USB_ENDPOINT Ep;
- PEI_EHC_QH *Qh;
- QH_HW *QhHw;
- PEI_EHC_QTD *Qtd;
+ USB_ENDPOINT Ep;
+ PEI_EHC_QH *Qh;
+ QH_HW *QhHw;
+ PEI_EHC_QTD *Qtd;
//
// Create an inactive Qtd to terminate the short packet read.
@@ -39,25 +39,25 @@ EhcCreateHelpQ ( return EFI_OUT_OF_RESOURCES;
}
- Qtd->QtdHw.Status = QTD_STAT_HALTED;
- Ehc->ShortReadStop = Qtd;
+ Qtd->QtdHw.Status = QTD_STAT_HALTED;
+ Ehc->ShortReadStop = Qtd;
//
// Create a QH to act as the EHC reclamation header.
// Set the header to loopback to itself.
//
- Ep.DevAddr = 0;
- Ep.EpAddr = 1;
- Ep.Direction = EfiUsbDataIn;
- Ep.DevSpeed = EFI_USB_SPEED_HIGH;
- Ep.MaxPacket = 64;
- Ep.HubAddr = 0;
- Ep.HubPort = 0;
- Ep.Toggle = 0;
- Ep.Type = EHC_BULK_TRANSFER;
- Ep.PollRate = 1;
-
- Qh = EhcCreateQh (Ehc, &Ep);
+ Ep.DevAddr = 0;
+ Ep.EpAddr = 1;
+ Ep.Direction = EfiUsbDataIn;
+ Ep.DevSpeed = EFI_USB_SPEED_HIGH;
+ Ep.MaxPacket = 64;
+ Ep.HubAddr = 0;
+ Ep.HubPort = 0;
+ Ep.Toggle = 0;
+ Ep.Type = EHC_BULK_TRANSFER;
+ Ep.PollRate = 1;
+
+ Qh = EhcCreateQh (Ehc, &Ep);
if (Qh == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -72,10 +72,10 @@ EhcCreateHelpQ ( //
// Create a dummy QH to act as the terminator for periodical schedule
//
- Ep.EpAddr = 2;
- Ep.Type = EHC_INT_TRANSFER_SYNC;
+ Ep.EpAddr = 2;
+ Ep.Type = EHC_INT_TRANSFER_SYNC;
- Qh = EhcCreateQh (Ehc, &Ep);
+ Qh = EhcCreateQh (Ehc, &Ep);
if (Qh == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -98,7 +98,7 @@ EhcCreateHelpQ ( **/
EFI_STATUS
EhcInitSched (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
VOID *Buf;
@@ -132,9 +132,9 @@ EhcInitSched ( return EFI_OUT_OF_RESOURCES;
}
- Ehc->PeriodFrame = Buf;
- Ehc->PeriodFrameMap = Map;
- Ehc->High32bitAddr = EHC_HIGH_32BIT (PhyAddr);
+ Ehc->PeriodFrame = Buf;
+ Ehc->PeriodFrameMap = Map;
+ Ehc->High32bitAddr = EHC_HIGH_32BIT (PhyAddr);
//
// Init memory pool management then create the helper
@@ -160,8 +160,8 @@ EhcInitSched ( //
// Initialize the frame list entries then set the registers
//
- Desc = (UINT32 *) Ehc->PeriodFrame;
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (PEI_EHC_QH));
+ Desc = (UINT32 *)Ehc->PeriodFrame;
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (PEI_EHC_QH));
for (Index = 0; Index < EHC_FRAME_LEN; Index++) {
Desc[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);
}
@@ -173,7 +173,7 @@ EhcInitSched ( // Only need to set the AsynListAddr register to
// the reclamation header
//
- PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ReclaimHead, sizeof (PEI_EHC_QH));
+ PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ReclaimHead, sizeof (PEI_EHC_QH));
EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, EHC_LOW_32BIT (PciAddr));
return EFI_SUCCESS;
}
@@ -186,7 +186,7 @@ EhcInitSched ( **/
VOID
EhcFreeSched (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
{
EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, 0);
@@ -231,24 +231,24 @@ EhcFreeSched ( **/
VOID
EhcLinkQhToAsync (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_EHC_QH *Qh
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_EHC_QH *Qh
)
{
- PEI_EHC_QH *Head;
+ PEI_EHC_QH *Head;
//
// Append the queue head after the reclaim header, then
// fix the hardware visiable parts (EHCI R1.0 page 72).
// ReclaimHead is always linked to the EHCI's AsynListAddr.
//
- Head = Ehc->ReclaimHead;
+ Head = Ehc->ReclaimHead;
- Qh->NextQh = Head->NextQh;
- Head->NextQh = Qh;
+ Qh->NextQh = Head->NextQh;
+ Head->NextQh = Qh;
- Qh->QhHw.HorizonLink = QH_LINK (Head, EHC_TYPE_QH, FALSE);;
- Head->QhHw.HorizonLink = QH_LINK (Qh, EHC_TYPE_QH, FALSE);
+ Qh->QhHw.HorizonLink = QH_LINK (Head, EHC_TYPE_QH, FALSE);
+ Head->QhHw.HorizonLink = QH_LINK (Qh, EHC_TYPE_QH, FALSE);
}
/**
@@ -261,11 +261,11 @@ EhcLinkQhToAsync ( **/
VOID
EhcUnlinkQhFromAsync (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_EHC_QH *Qh
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_EHC_QH *Qh
)
{
- PEI_EHC_QH *Head;
+ PEI_EHC_QH *Head;
ASSERT (Ehc->ReclaimHead->NextQh == Qh);
@@ -274,12 +274,12 @@ EhcUnlinkQhFromAsync ( // visiable part: Only need to loopback the ReclaimHead. The Qh
// is pointing to ReclaimHead (which is staill in the list).
//
- Head = Ehc->ReclaimHead;
+ Head = Ehc->ReclaimHead;
- Head->NextQh = Qh->NextQh;
- Qh->NextQh = NULL;
+ Head->NextQh = Qh->NextQh;
+ Qh->NextQh = NULL;
- Head->QhHw.HorizonLink = QH_LINK (Head, EHC_TYPE_QH, FALSE);
+ Head->QhHw.HorizonLink = QH_LINK (Head, EHC_TYPE_QH, FALSE);
//
// Set and wait the door bell to synchronize with the hardware
@@ -302,22 +302,22 @@ EhcUnlinkQhFromAsync ( **/
BOOLEAN
EhcCheckUrbResult (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_URB *Urb
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_URB *Urb
)
{
- EFI_LIST_ENTRY *Entry;
- PEI_EHC_QTD *Qtd;
- QTD_HW *QtdHw;
- UINT8 State;
- BOOLEAN Finished;
+ EFI_LIST_ENTRY *Entry;
+ PEI_EHC_QTD *Qtd;
+ QTD_HW *QtdHw;
+ UINT8 State;
+ BOOLEAN Finished;
ASSERT ((Ehc != NULL) && (Urb != NULL) && (Urb->Qh != NULL));
- Finished = TRUE;
- Urb->Completed = 0;
+ Finished = TRUE;
+ Urb->Completed = 0;
- Urb->Result = EFI_USB_NOERROR;
+ Urb->Result = EFI_USB_NOERROR;
if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {
Urb->Result |= EFI_USB_ERR_SYSTEM;
@@ -327,7 +327,7 @@ EhcCheckUrbResult ( BASE_LIST_FOR_EACH (Entry, &Urb->Qh->Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, PEI_EHC_QTD, QtdList);
QtdHw = &Qtd->QtdHw;
- State = (UINT8) QtdHw->Status;
+ State = (UINT8)QtdHw->Status;
if (EHC_BIT_IS_SET (State, QTD_STAT_HALTED)) {
//
@@ -352,7 +352,6 @@ EhcCheckUrbResult ( Finished = TRUE;
goto ON_EXIT;
-
} else if (EHC_BIT_IS_SET (State, QTD_STAT_ACTIVE)) {
//
// The QTD is still active, no need to check furthur.
@@ -361,7 +360,6 @@ EhcCheckUrbResult ( Finished = FALSE;
goto ON_EXIT;
-
} else {
//
// This QTD is finished OK or met short packet read. Update the
@@ -372,7 +370,7 @@ EhcCheckUrbResult ( }
if ((QtdHw->TotalBytes != 0) && (QtdHw->Pid == QTD_PID_INPUT)) {
- //EHC_DUMP_QH ((Urb->Qh, "Short packet read", FALSE));
+ // EHC_DUMP_QH ((Urb->Qh, "Short packet read", FALSE));
//
// Short packet read condition. If it isn't a setup transfer,
@@ -381,7 +379,6 @@ EhcCheckUrbResult ( // Status Stage of the setup transfer to get the finial result
//
if (QtdHw->AltNext == QTD_LINK (Ehc->ShortReadStop, FALSE)) {
-
Finished = TRUE;
goto ON_EXIT;
}
@@ -399,7 +396,7 @@ ON_EXIT: // NOTICE: don't move DT update before the loop, otherwise there is
// a race condition that DT is wrong.
//
- Urb->DataToggle = (UINT8) Urb->Qh->QhHw.DataToggle;
+ Urb->DataToggle = (UINT8)Urb->Qh->QhHw.DataToggle;
return Finished;
}
@@ -418,19 +415,19 @@ ON_EXIT: **/
EFI_STATUS
EhcExecTransfer (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_URB *Urb,
- IN UINTN TimeOut
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_URB *Urb,
+ IN UINTN TimeOut
)
{
- EFI_STATUS Status;
- UINTN Index;
- UINTN Loop;
- BOOLEAN Finished;
- BOOLEAN InfiniteLoop;
-
- Status = EFI_SUCCESS;
- Loop = TimeOut * EHC_1_MILLISECOND;
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN Loop;
+ BOOLEAN Finished;
+ BOOLEAN InfiniteLoop;
+
+ Status = EFI_SUCCESS;
+ Loop = TimeOut * EHC_1_MILLISECOND;
Finished = FALSE;
InfiniteLoop = FALSE;
@@ -460,4 +457,3 @@ EhcExecTransfer ( return Status;
}
-
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.h b/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.h index 60f8cb8..6cba2d3 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.h +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhciSched.h @@ -21,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
EFI_STATUS
EhcInitSched (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -33,7 +33,7 @@ EhcInitSched ( **/
VOID
EhcFreeSched (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -50,8 +50,8 @@ EhcFreeSched ( **/
VOID
EhcLinkQhToAsync (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_EHC_QH *Qh
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_EHC_QH *Qh
)
;
@@ -65,8 +65,8 @@ EhcLinkQhToAsync ( **/
VOID
EhcUnlinkQhFromAsync (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_EHC_QH *Qh
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_EHC_QH *Qh
)
;
@@ -84,9 +84,9 @@ EhcUnlinkQhFromAsync ( **/
EFI_STATUS
EhcExecTransfer (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_URB *Urb,
- IN UINTN TimeOut
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_URB *Urb,
+ IN UINTN TimeOut
)
;
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.c b/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.c index df512ed..1ad7f3a 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.c +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.c @@ -27,19 +27,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
PEI_EHC_QTD *
EhcCreateQtd (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT8 *Data,
- IN UINTN DataLen,
- IN UINT8 PktId,
- IN UINT8 Toggle,
- IN UINTN MaxPacket
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT8 *Data,
+ IN UINTN DataLen,
+ IN UINT8 PktId,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket
)
{
- PEI_EHC_QTD *Qtd;
- QTD_HW *QtdHw;
- UINTN Index;
- UINTN Len;
- UINTN ThisBufLen;
+ PEI_EHC_QTD *Qtd;
+ QTD_HW *QtdHw;
+ UINTN Index;
+ UINTN Len;
+ UINTN ThisBufLen;
ASSERT (Ehc != NULL);
@@ -49,9 +49,9 @@ EhcCreateQtd ( return NULL;
}
- Qtd->Signature = EHC_QTD_SIG;
- Qtd->Data = Data;
- Qtd->DataLen = 0;
+ Qtd->Signature = EHC_QTD_SIG;
+ Qtd->Data = Data;
+ Qtd->DataLen = 0;
InitializeListHead (&Qtd->QtdList);
@@ -77,17 +77,17 @@ EhcCreateQtd ( // compute the offset and clear Reserved fields. This is already
// done in the data point.
//
- QtdHw->Page[Index] = EHC_LOW_32BIT (Data);
- QtdHw->PageHigh[Index] = EHC_HIGH_32BIT (Data);
+ QtdHw->Page[Index] = EHC_LOW_32BIT (Data);
+ QtdHw->PageHigh[Index] = EHC_HIGH_32BIT (Data);
- ThisBufLen = QTD_BUF_LEN - (EHC_LOW_32BIT (Data) & QTD_BUF_MASK);
+ ThisBufLen = QTD_BUF_LEN - (EHC_LOW_32BIT (Data) & QTD_BUF_MASK);
if (Len + ThisBufLen >= DataLen) {
Len = DataLen;
break;
}
- Len += ThisBufLen;
+ Len += ThisBufLen;
Data += ThisBufLen;
}
@@ -101,7 +101,7 @@ EhcCreateQtd ( Len = Len - Len % MaxPacket;
}
- QtdHw->TotalBytes = (UINT32) Len;
+ QtdHw->TotalBytes = (UINT32)Len;
Qtd->DataLen = Len;
}
@@ -121,8 +121,8 @@ EhcCreateQtd ( **/
VOID
EhcInitIntQh (
- IN USB_ENDPOINT *Ep,
- IN QH_HW *QhHw
+ IN USB_ENDPOINT *Ep,
+ IN QH_HW *QhHw
)
{
//
@@ -134,7 +134,7 @@ EhcInitIntQh ( //
if (Ep->DevSpeed == EFI_USB_SPEED_HIGH) {
QhHw->SMask = QH_MICROFRAME_0;
- return ;
+ return;
}
//
@@ -163,12 +163,12 @@ EhcInitIntQh ( **/
PEI_EHC_QH *
EhcCreateQh (
- IN PEI_USB2_HC_DEV *Ehci,
- IN USB_ENDPOINT *Ep
+ IN PEI_USB2_HC_DEV *Ehci,
+ IN USB_ENDPOINT *Ep
)
{
- PEI_EHC_QH *Qh;
- QH_HW *QhHw;
+ PEI_EHC_QH *Qh;
+ QH_HW *QhHw;
Qh = UsbHcAllocateMem (Ehci, Ehci->MemPool, sizeof (PEI_EHC_QH));
@@ -176,62 +176,63 @@ EhcCreateQh ( return NULL;
}
- Qh->Signature = EHC_QH_SIG;
- Qh->NextQh = NULL;
- Qh->Interval = Ep->PollRate;
+ Qh->Signature = EHC_QH_SIG;
+ Qh->NextQh = NULL;
+ Qh->Interval = Ep->PollRate;
InitializeListHead (&Qh->Qtds);
- QhHw = &Qh->QhHw;
- QhHw->HorizonLink = QH_LINK (NULL, 0, TRUE);
- QhHw->DeviceAddr = Ep->DevAddr;
- QhHw->Inactive = 0;
- QhHw->EpNum = Ep->EpAddr;
- QhHw->EpSpeed = Ep->DevSpeed;
- QhHw->DtCtrl = 0;
- QhHw->ReclaimHead = 0;
- QhHw->MaxPacketLen = (UINT32) Ep->MaxPacket;
- QhHw->CtrlEp = 0;
- QhHw->NakReload = QH_NAK_RELOAD;
- QhHw->HubAddr = Ep->HubAddr;
- QhHw->PortNum = Ep->HubPort;
- QhHw->Multiplier = 1;
- QhHw->DataToggle = Ep->Toggle;
+ QhHw = &Qh->QhHw;
+ QhHw->HorizonLink = QH_LINK (NULL, 0, TRUE);
+ QhHw->DeviceAddr = Ep->DevAddr;
+ QhHw->Inactive = 0;
+ QhHw->EpNum = Ep->EpAddr;
+ QhHw->EpSpeed = Ep->DevSpeed;
+ QhHw->DtCtrl = 0;
+ QhHw->ReclaimHead = 0;
+ QhHw->MaxPacketLen = (UINT32)Ep->MaxPacket;
+ QhHw->CtrlEp = 0;
+ QhHw->NakReload = QH_NAK_RELOAD;
+ QhHw->HubAddr = Ep->HubAddr;
+ QhHw->PortNum = Ep->HubPort;
+ QhHw->Multiplier = 1;
+ QhHw->DataToggle = Ep->Toggle;
if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
QhHw->Status |= QTD_STAT_DO_SS;
}
switch (Ep->Type) {
- case EHC_CTRL_TRANSFER:
- //
- // Special initialization for the control transfer:
- // 1. Control transfer initialize data toggle from each QTD
- // 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
- //
- QhHw->DtCtrl = 1;
+ case EHC_CTRL_TRANSFER:
+ //
+ // Special initialization for the control transfer:
+ // 1. Control transfer initialize data toggle from each QTD
+ // 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
+ //
+ QhHw->DtCtrl = 1;
- if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
- QhHw->CtrlEp = 1;
- }
- break;
+ if (Ep->DevSpeed != EFI_USB_SPEED_HIGH) {
+ QhHw->CtrlEp = 1;
+ }
- case EHC_INT_TRANSFER_ASYNC:
- case EHC_INT_TRANSFER_SYNC:
- //
- // Special initialization for the interrupt transfer
- // to set the S-Mask and C-Mask
- //
- QhHw->NakReload = 0;
- EhcInitIntQh (Ep, QhHw);
- break;
+ break;
- case EHC_BULK_TRANSFER:
- if ((Ep->DevSpeed == EFI_USB_SPEED_HIGH) && (Ep->Direction == EfiUsbDataOut)) {
- QhHw->Status |= QTD_STAT_DO_PING;
- }
+ case EHC_INT_TRANSFER_ASYNC:
+ case EHC_INT_TRANSFER_SYNC:
+ //
+ // Special initialization for the interrupt transfer
+ // to set the S-Mask and C-Mask
+ //
+ QhHw->NakReload = 0;
+ EhcInitIntQh (Ep, QhHw);
+ break;
+
+ case EHC_BULK_TRANSFER:
+ if ((Ep->DevSpeed == EFI_USB_SPEED_HIGH) && (Ep->Direction == EfiUsbDataOut)) {
+ QhHw->Status |= QTD_STAT_DO_PING;
+ }
- break;
+ break;
}
return Qh;
@@ -252,10 +253,10 @@ EhcCreateQh ( **/
UINTN
EhcConvertPollRate (
- IN UINTN Interval
+ IN UINTN Interval
)
{
- UINTN BitCount;
+ UINTN BitCount;
if (Interval == 0) {
return 1;
@@ -283,13 +284,13 @@ EhcConvertPollRate ( **/
VOID
EhcFreeQtds (
- IN PEI_USB2_HC_DEV *Ehc,
- IN EFI_LIST_ENTRY *Qtds
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN EFI_LIST_ENTRY *Qtds
)
{
- EFI_LIST_ENTRY *Entry;
- EFI_LIST_ENTRY *Next;
- PEI_EHC_QTD *Qtd;
+ EFI_LIST_ENTRY *Entry;
+ EFI_LIST_ENTRY *Next;
+ PEI_EHC_QTD *Qtd;
BASE_LIST_FOR_EACH_SAFE (Entry, Next, Qtds) {
Qtd = EFI_LIST_CONTAINER (Entry, PEI_EHC_QTD, QtdList);
@@ -308,8 +309,8 @@ EhcFreeQtds ( **/
VOID
EhcFreeUrb (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_URB *Urb
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_URB *Urb
)
{
if (Urb->RequestPhy != NULL) {
@@ -342,20 +343,20 @@ EhcFreeUrb ( **/
EFI_STATUS
EhcCreateQtds (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_URB *Urb
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_URB *Urb
)
{
- USB_ENDPOINT *Ep;
- PEI_EHC_QH *Qh;
- PEI_EHC_QTD *Qtd;
- PEI_EHC_QTD *StatusQtd;
- PEI_EHC_QTD *NextQtd;
- EFI_LIST_ENTRY *Entry;
- UINT32 AlterNext;
- UINT8 Toggle;
- UINTN Len;
- UINT8 Pid;
+ USB_ENDPOINT *Ep;
+ PEI_EHC_QH *Qh;
+ PEI_EHC_QTD *Qtd;
+ PEI_EHC_QTD *StatusQtd;
+ PEI_EHC_QTD *NextQtd;
+ EFI_LIST_ENTRY *Entry;
+ UINT32 AlterNext;
+ UINT8 Toggle;
+ UINTN Len;
+ UINT8 Pid;
ASSERT ((Urb != NULL) && (Urb->Qh != NULL));
@@ -428,7 +429,7 @@ EhcCreateQtds ( while (Len < Urb->DataLen) {
Qtd = EhcCreateQtd (
Ehc,
- (UINT8 *) Urb->DataPhy + Len,
+ (UINT8 *)Urb->DataPhy + Len,
Urb->DataLen - Len,
Pid,
Toggle,
@@ -446,7 +447,7 @@ EhcCreateQtds ( // Switch the Toggle bit if odd number of packets are included in the QTD.
//
if (((Qtd->DataLen + Ep->MaxPacket - 1) / Ep->MaxPacket) % 2) {
- Toggle = (UINT8) (1 - Toggle);
+ Toggle = (UINT8)(1 - Toggle);
}
Len += Qtd->DataLen;
@@ -472,15 +473,15 @@ EhcCreateQtds ( break;
}
- NextQtd = EFI_LIST_CONTAINER (Entry->ForwardLink, PEI_EHC_QTD, QtdList);
- Qtd->QtdHw.NextQtd = QTD_LINK (NextQtd, FALSE);
+ NextQtd = EFI_LIST_CONTAINER (Entry->ForwardLink, PEI_EHC_QTD, QtdList);
+ Qtd->QtdHw.NextQtd = QTD_LINK (NextQtd, FALSE);
}
//
// Link the QTDs to the queue head
//
- NextQtd = EFI_LIST_CONTAINER (Qh->Qtds.ForwardLink, PEI_EHC_QTD, QtdList);
- Qh->QhHw.NextQtd = QTD_LINK (NextQtd, FALSE);
+ NextQtd = EFI_LIST_CONTAINER (Qh->Qtds.ForwardLink, PEI_EHC_QTD, QtdList);
+ Qh->QhHw.NextQtd = QTD_LINK (NextQtd, FALSE);
return EFI_SUCCESS;
ON_ERROR:
@@ -511,63 +512,63 @@ ON_ERROR: **/
PEI_URB *
EhcCreateUrb (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT8 DevAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINT8 Toggle,
- IN UINTN MaxPacket,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context,
- IN UINTN Interval
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context,
+ IN UINTN Interval
)
{
- USB_ENDPOINT *Ep;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- EDKII_IOMMU_OPERATION MapOp;
- EFI_STATUS Status;
- UINTN Len;
- PEI_URB *Urb;
- VOID *Map;
+ USB_ENDPOINT *Ep;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ EDKII_IOMMU_OPERATION MapOp;
+ EFI_STATUS Status;
+ UINTN Len;
+ PEI_URB *Urb;
+ VOID *Map;
Map = NULL;
- Urb = Ehc->Urb;
- Urb->Signature = EHC_URB_SIG;
+ Urb = Ehc->Urb;
+ Urb->Signature = EHC_URB_SIG;
InitializeListHead (&Urb->UrbList);
- Ep = &Urb->Ep;
- Ep->DevAddr = DevAddr;
- Ep->EpAddr = (UINT8) (EpAddr & 0x0F);
- Ep->Direction = (((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);
- Ep->DevSpeed = DevSpeed;
- Ep->MaxPacket = MaxPacket;
+ Ep = &Urb->Ep;
+ Ep->DevAddr = DevAddr;
+ Ep->EpAddr = (UINT8)(EpAddr & 0x0F);
+ Ep->Direction = (((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);
+ Ep->DevSpeed = DevSpeed;
+ Ep->MaxPacket = MaxPacket;
- Ep->HubAddr = 0;
- Ep->HubPort = 0;
+ Ep->HubAddr = 0;
+ Ep->HubPort = 0;
if (DevSpeed != EFI_USB_SPEED_HIGH) {
ASSERT (Hub != NULL);
- Ep->HubAddr = Hub->TranslatorHubAddress;
- Ep->HubPort = Hub->TranslatorPortNumber;
+ Ep->HubAddr = Hub->TranslatorHubAddress;
+ Ep->HubPort = Hub->TranslatorPortNumber;
}
- Ep->Toggle = Toggle;
- Ep->Type = Type;
- Ep->PollRate = EhcConvertPollRate (Interval);
+ Ep->Toggle = Toggle;
+ Ep->Type = Type;
+ Ep->PollRate = EhcConvertPollRate (Interval);
- Urb->Request = Request;
- Urb->Data = Data;
- Urb->DataLen = DataLen;
- Urb->Callback = Callback;
- Urb->Context = Context;
- Urb->Qh = EhcCreateQh (Ehc, &Urb->Ep);
+ Urb->Request = Request;
+ Urb->Data = Data;
+ Urb->DataLen = DataLen;
+ Urb->Callback = Callback;
+ Urb->Context = Context;
+ Urb->Qh = EhcCreateQh (Ehc, &Urb->Ep);
if (Urb->Qh == NULL) {
goto ON_ERROR;
@@ -575,27 +576,27 @@ EhcCreateUrb ( Urb->RequestPhy = NULL;
Urb->RequestMap = NULL;
- Urb->DataPhy = NULL;
- Urb->DataMap = NULL;
+ Urb->DataPhy = NULL;
+ Urb->DataMap = NULL;
//
// Map the request and user data
//
if (Request != NULL) {
- Len = sizeof (EFI_USB_DEVICE_REQUEST);
- MapOp = EdkiiIoMmuOperationBusMasterRead;
- Status = IoMmuMap (Ehc->IoMmu, MapOp, Request, &Len, &PhyAddr, &Map);
+ Len = sizeof (EFI_USB_DEVICE_REQUEST);
+ MapOp = EdkiiIoMmuOperationBusMasterRead;
+ Status = IoMmuMap (Ehc->IoMmu, MapOp, Request, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != sizeof (EFI_USB_DEVICE_REQUEST))) {
goto ON_ERROR;
}
- Urb->RequestPhy = (VOID *) ((UINTN) PhyAddr);
+ Urb->RequestPhy = (VOID *)((UINTN)PhyAddr);
Urb->RequestMap = Map;
}
if (Data != NULL) {
- Len = DataLen;
+ Len = DataLen;
if (Ep->Direction == EfiUsbDataIn) {
MapOp = EdkiiIoMmuOperationBusMasterWrite;
@@ -603,14 +604,14 @@ EhcCreateUrb ( MapOp = EdkiiIoMmuOperationBusMasterRead;
}
- Status = IoMmuMap (Ehc->IoMmu, MapOp, Data, &Len, &PhyAddr, &Map);
+ Status = IoMmuMap (Ehc->IoMmu, MapOp, Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != DataLen)) {
goto ON_ERROR;
}
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
- Urb->DataMap = Map;
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
+ Urb->DataMap = Map;
}
Status = EhcCreateQtds (Ehc, Urb);
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.h b/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.h index 756b663..9b8aa5d 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.h +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhciUrb.h @@ -10,60 +10,60 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_EHCI_URB_H_
#define _EFI_EHCI_URB_H_
-typedef struct _PEI_EHC_QTD PEI_EHC_QTD;
-typedef struct _PEI_EHC_QH PEI_EHC_QH;
-typedef struct _PEI_URB PEI_URB;
+typedef struct _PEI_EHC_QTD PEI_EHC_QTD;
+typedef struct _PEI_EHC_QH PEI_EHC_QH;
+typedef struct _PEI_URB PEI_URB;
#define EHC_CTRL_TRANSFER 0x01
#define EHC_BULK_TRANSFER 0x02
#define EHC_INT_TRANSFER_SYNC 0x04
#define EHC_INT_TRANSFER_ASYNC 0x08
-#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
-#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
-#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
+#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
+#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
+#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
//
// Hardware related bit definitions
//
-#define EHC_TYPE_ITD 0x00
-#define EHC_TYPE_QH 0x02
-#define EHC_TYPE_SITD 0x04
-#define EHC_TYPE_FSTN 0x06
-
-#define QH_NAK_RELOAD 3
-#define QH_HSHBW_MULTI 1
-
-#define QTD_MAX_ERR 3
-#define QTD_PID_OUTPUT 0x00
-#define QTD_PID_INPUT 0x01
-#define QTD_PID_SETUP 0x02
-
-#define QTD_STAT_DO_OUT 0
-#define QTD_STAT_DO_SS 0
-#define QTD_STAT_DO_PING 0x01
-#define QTD_STAT_DO_CS 0x02
-#define QTD_STAT_TRANS_ERR 0x08
-#define QTD_STAT_BABBLE_ERR 0x10
-#define QTD_STAT_BUFF_ERR 0x20
-#define QTD_STAT_HALTED 0x40
-#define QTD_STAT_ACTIVE 0x80
-#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
-
-#define QTD_MAX_BUFFER 4
-#define QTD_BUF_LEN 4096
-#define QTD_BUF_MASK 0x0FFF
-
-#define QH_MICROFRAME_0 0x01
-#define QH_MICROFRAME_1 0x02
-#define QH_MICROFRAME_2 0x04
-#define QH_MICROFRAME_3 0x08
-#define QH_MICROFRAME_4 0x10
-#define QH_MICROFRAME_5 0x20
-#define QH_MICROFRAME_6 0x40
-#define QH_MICROFRAME_7 0x80
-
-#define USB_ERR_SHORT_PACKET 0x200
+#define EHC_TYPE_ITD 0x00
+#define EHC_TYPE_QH 0x02
+#define EHC_TYPE_SITD 0x04
+#define EHC_TYPE_FSTN 0x06
+
+#define QH_NAK_RELOAD 3
+#define QH_HSHBW_MULTI 1
+
+#define QTD_MAX_ERR 3
+#define QTD_PID_OUTPUT 0x00
+#define QTD_PID_INPUT 0x01
+#define QTD_PID_SETUP 0x02
+
+#define QTD_STAT_DO_OUT 0
+#define QTD_STAT_DO_SS 0
+#define QTD_STAT_DO_PING 0x01
+#define QTD_STAT_DO_CS 0x02
+#define QTD_STAT_TRANS_ERR 0x08
+#define QTD_STAT_BABBLE_ERR 0x10
+#define QTD_STAT_BUFF_ERR 0x20
+#define QTD_STAT_HALTED 0x40
+#define QTD_STAT_ACTIVE 0x80
+#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
+
+#define QTD_MAX_BUFFER 4
+#define QTD_BUF_LEN 4096
+#define QTD_BUF_MASK 0x0FFF
+
+#define QH_MICROFRAME_0 0x01
+#define QH_MICROFRAME_1 0x02
+#define QH_MICROFRAME_2 0x04
+#define QH_MICROFRAME_3 0x08
+#define QH_MICROFRAME_4 0x10
+#define QH_MICROFRAME_5 0x20
+#define QH_MICROFRAME_6 0x40
+#define QH_MICROFRAME_7 0x80
+
+#define USB_ERR_SHORT_PACKET 0x200
//
// Fill in the hardware link point: pass in a EHC_QH/QH_HW
@@ -72,7 +72,7 @@ typedef struct _PEI_URB PEI_URB; #define QH_LINK(Addr, Type, Term) \
((UINT32) ((EHC_LOW_32BIT (Addr) & 0xFFFFFFE0) | (Type) | ((Term) ? 1 : 0)))
-#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
+#define QTD_LINK(Addr, Term) QH_LINK((Addr), 0, (Term))
//
// The defination of EHCI hardware used data structure for
@@ -82,77 +82,76 @@ typedef struct _PEI_URB PEI_URB; //
#pragma pack(1)
typedef struct {
- UINT32 NextQtd;
- UINT32 AltNext;
-
- UINT32 Status : 8;
- UINT32 Pid : 2;
- UINT32 ErrCnt : 2;
- UINT32 CurPage : 3;
- UINT32 Ioc : 1;
- UINT32 TotalBytes : 15;
- UINT32 DataToggle : 1;
-
- UINT32 Page[5];
- UINT32 PageHigh[5];
+ UINT32 NextQtd;
+ UINT32 AltNext;
+
+ UINT32 Status : 8;
+ UINT32 Pid : 2;
+ UINT32 ErrCnt : 2;
+ UINT32 CurPage : 3;
+ UINT32 Ioc : 1;
+ UINT32 TotalBytes : 15;
+ UINT32 DataToggle : 1;
+
+ UINT32 Page[5];
+ UINT32 PageHigh[5];
} QTD_HW;
typedef struct {
- UINT32 HorizonLink;
+ UINT32 HorizonLink;
//
// Endpoint capabilities/Characteristics DWord 1 and DWord 2
//
- UINT32 DeviceAddr : 7;
- UINT32 Inactive : 1;
- UINT32 EpNum : 4;
- UINT32 EpSpeed : 2;
- UINT32 DtCtrl : 1;
- UINT32 ReclaimHead : 1;
- UINT32 MaxPacketLen : 11;
- UINT32 CtrlEp : 1;
- UINT32 NakReload : 4;
-
- UINT32 SMask : 8;
- UINT32 CMask : 8;
- UINT32 HubAddr : 7;
- UINT32 PortNum : 7;
- UINT32 Multiplier : 2;
+ UINT32 DeviceAddr : 7;
+ UINT32 Inactive : 1;
+ UINT32 EpNum : 4;
+ UINT32 EpSpeed : 2;
+ UINT32 DtCtrl : 1;
+ UINT32 ReclaimHead : 1;
+ UINT32 MaxPacketLen : 11;
+ UINT32 CtrlEp : 1;
+ UINT32 NakReload : 4;
+
+ UINT32 SMask : 8;
+ UINT32 CMask : 8;
+ UINT32 HubAddr : 7;
+ UINT32 PortNum : 7;
+ UINT32 Multiplier : 2;
//
// Transaction execution overlay area
//
- UINT32 CurQtd;
- UINT32 NextQtd;
- UINT32 AltQtd;
-
- UINT32 Status : 8;
- UINT32 Pid : 2;
- UINT32 ErrCnt : 2;
- UINT32 CurPage : 3;
- UINT32 Ioc : 1;
- UINT32 TotalBytes : 15;
- UINT32 DataToggle : 1;
-
- UINT32 Page[5];
- UINT32 PageHigh[5];
+ UINT32 CurQtd;
+ UINT32 NextQtd;
+ UINT32 AltQtd;
+
+ UINT32 Status : 8;
+ UINT32 Pid : 2;
+ UINT32 ErrCnt : 2;
+ UINT32 CurPage : 3;
+ UINT32 Ioc : 1;
+ UINT32 TotalBytes : 15;
+ UINT32 DataToggle : 1;
+
+ UINT32 Page[5];
+ UINT32 PageHigh[5];
} QH_HW;
#pragma pack()
-
//
// Endpoint address and its capabilities
//
typedef struct _USB_ENDPOINT {
- UINT8 DevAddr;
- UINT8 EpAddr; // Endpoint address, no direction encoded in
- EFI_USB_DATA_DIRECTION Direction;
- UINT8 DevSpeed;
- UINTN MaxPacket;
- UINT8 HubAddr;
- UINT8 HubPort;
- UINT8 Toggle; // Data toggle, not used for control transfer
- UINTN Type;
- UINTN PollRate; // Polling interval used by EHCI
+ UINT8 DevAddr;
+ UINT8 EpAddr; // Endpoint address, no direction encoded in
+ EFI_USB_DATA_DIRECTION Direction;
+ UINT8 DevSpeed;
+ UINTN MaxPacket;
+ UINT8 HubAddr;
+ UINT8 HubPort;
+ UINT8 Toggle; // Data toggle, not used for control transfer
+ UINTN Type;
+ UINTN PollRate; // Polling interval used by EHCI
} USB_ENDPOINT;
//
@@ -160,15 +159,13 @@ typedef struct _USB_ENDPOINT { // QTD generated from a URB. Don't add fields before QtdHw.
//
struct _PEI_EHC_QTD {
- QTD_HW QtdHw;
- UINT32 Signature;
- EFI_LIST_ENTRY QtdList; // The list of QTDs to one end point
- UINT8 *Data; // Buffer of the original data
- UINTN DataLen; // Original amount of data in this QTD
+ QTD_HW QtdHw;
+ UINT32 Signature;
+ EFI_LIST_ENTRY QtdList; // The list of QTDs to one end point
+ UINT8 *Data; // Buffer of the original data
+ UINTN DataLen; // Original amount of data in this QTD
};
-
-
//
// Software QH structure. All three different transaction types
// supported by UEFI USB, that is the control/bulk/interrupt
@@ -185,11 +182,11 @@ struct _PEI_EHC_QTD { // as the reclamation header. New transfer is inserted after this QH.
//
struct _PEI_EHC_QH {
- QH_HW QhHw;
- UINT32 Signature;
- PEI_EHC_QH *NextQh; // The queue head pointed to by horizontal link
- EFI_LIST_ENTRY Qtds; // The list of QTDs to this queue head
- UINTN Interval;
+ QH_HW QhHw;
+ UINT32 Signature;
+ PEI_EHC_QH *NextQh; // The queue head pointed to by horizontal link
+ EFI_LIST_ENTRY Qtds; // The list of QTDs to this queue head
+ UINTN Interval;
};
//
@@ -197,34 +194,34 @@ struct _PEI_EHC_QH { // usb requests.
//
struct _PEI_URB {
- UINT32 Signature;
- EFI_LIST_ENTRY UrbList;
+ UINT32 Signature;
+ EFI_LIST_ENTRY UrbList;
//
// Transaction information
//
- USB_ENDPOINT Ep;
- EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
- VOID *RequestPhy; // Address of the mapped request
- VOID *RequestMap;
- VOID *Data;
- UINTN DataLen;
- VOID *DataPhy; // Address of the mapped user data
- VOID *DataMap;
- EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
- VOID *Context;
+ USB_ENDPOINT Ep;
+ EFI_USB_DEVICE_REQUEST *Request; // Control transfer only
+ VOID *RequestPhy; // Address of the mapped request
+ VOID *RequestMap;
+ VOID *Data;
+ UINTN DataLen;
+ VOID *DataPhy; // Address of the mapped user data
+ VOID *DataMap;
+ EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
+ VOID *Context;
//
// Schedule data
//
- PEI_EHC_QH *Qh;
+ PEI_EHC_QH *Qh;
//
// Transaction result
//
- UINT32 Result;
- UINTN Completed; // completed data length
- UINT8 DataToggle;
+ UINT32 Result;
+ UINTN Completed; // completed data length
+ UINT8 DataToggle;
};
/**
@@ -243,12 +240,12 @@ struct _PEI_URB { **/
PEI_EHC_QTD *
EhcCreateQtd (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT8 *Data,
- IN UINTN DataLen,
- IN UINT8 PktId,
- IN UINT8 Toggle,
- IN UINTN MaxPacket
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT8 *Data,
+ IN UINTN DataLen,
+ IN UINT8 PktId,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket
)
;
@@ -263,8 +260,8 @@ EhcCreateQtd ( **/
PEI_EHC_QH *
EhcCreateQh (
- IN PEI_USB2_HC_DEV *Ehci,
- IN USB_ENDPOINT *Ep
+ IN PEI_USB2_HC_DEV *Ehci,
+ IN USB_ENDPOINT *Ep
)
;
@@ -277,8 +274,8 @@ EhcCreateQh ( **/
VOID
EhcFreeUrb (
- IN PEI_USB2_HC_DEV *Ehc,
- IN PEI_URB *Urb
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN PEI_URB *Urb
)
;
@@ -305,20 +302,21 @@ EhcFreeUrb ( **/
PEI_URB *
EhcCreateUrb (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT8 DevAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINT8 Toggle,
- IN UINTN MaxPacket,
- IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context,
- IN UINTN Interval
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT8 DevAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINT8 Toggle,
+ IN UINTN MaxPacket,
+ IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Hub,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context,
+ IN UINTN Interval
)
;
+
#endif
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.c b/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.c index 269b3ed..4b1fdce 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.c +++ b/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.c @@ -22,30 +22,31 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
USBHC_MEM_BLOCK *
UsbHcAllocMemBlock (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Pages
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Pages
)
{
- USBHC_MEM_BLOCK *Block;
- VOID *BufHost;
- VOID *Mapping;
- EFI_PHYSICAL_ADDRESS MappedAddr;
- EFI_STATUS Status;
- UINTN PageNumber;
- EFI_PHYSICAL_ADDRESS TempPtr;
-
- Mapping = NULL;
- PageNumber = sizeof(USBHC_MEM_BLOCK)/PAGESIZE +1;
- Status = PeiServicesAllocatePages (
- EfiBootServicesCode,
- PageNumber,
- &TempPtr
- );
+ USBHC_MEM_BLOCK *Block;
+ VOID *BufHost;
+ VOID *Mapping;
+ EFI_PHYSICAL_ADDRESS MappedAddr;
+ EFI_STATUS Status;
+ UINTN PageNumber;
+ EFI_PHYSICAL_ADDRESS TempPtr;
+
+ Mapping = NULL;
+ PageNumber = sizeof (USBHC_MEM_BLOCK)/PAGESIZE +1;
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesCode,
+ PageNumber,
+ &TempPtr
+ );
if (EFI_ERROR (Status)) {
- return NULL;
+ return NULL;
}
+
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
//
@@ -54,34 +55,36 @@ UsbHcAllocMemBlock ( //
ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
- Block = (USBHC_MEM_BLOCK*)(UINTN)TempPtr;
- Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
- Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
+ Block = (USBHC_MEM_BLOCK *)(UINTN)TempPtr;
+ Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
+ Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8);
PageNumber = (Block->BitsLen)/PAGESIZE +1;
- Status = PeiServicesAllocatePages (
- EfiBootServicesCode,
- PageNumber,
- &TempPtr
- );
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesCode,
+ PageNumber,
+ &TempPtr
+ );
+
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
- if (EFI_ERROR (Status)) {
- return NULL;
- }
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
- Block->Bits = (UINT8 *)(UINTN)TempPtr;
+ Block->Bits = (UINT8 *)(UINTN)TempPtr;
Status = IoMmuAllocateBuffer (
Ehc->IoMmu,
Pages,
- (VOID **) &BufHost,
+ (VOID **)&BufHost,
&MappedAddr,
&Mapping
);
if (EFI_ERROR (Status)) {
return NULL;
}
+
ZeroMem (BufHost, Pages*EFI_PAGE_SIZE);
//
@@ -89,16 +92,15 @@ UsbHcAllocMemBlock ( // should be restricted into the same 4G
//
if (Pool->Check4G && (Pool->Which4G != USB_HC_HIGH_32BIT (MappedAddr))) {
- return NULL;
+ return NULL;
}
- Block->BufHost = BufHost;
- Block->Buf = (UINT8 *) ((UINTN) MappedAddr);
- Block->Mapping = Mapping;
- Block->Next = NULL;
+ Block->BufHost = BufHost;
+ Block->Buf = (UINT8 *)((UINTN)MappedAddr);
+ Block->Mapping = Mapping;
+ Block->Next = NULL;
return Block;
-
}
/**
@@ -111,9 +113,9 @@ UsbHcAllocMemBlock ( **/
VOID
UsbHcFreeMemBlock (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool,
- IN USBHC_MEM_BLOCK *Block
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool,
+ IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Pool != NULL) && (Block != NULL));
@@ -133,22 +135,22 @@ UsbHcFreeMemBlock ( **/
VOID *
UsbHcAllocMemFromBlock (
- IN USBHC_MEM_BLOCK *Block,
- IN UINTN Units
+ IN USBHC_MEM_BLOCK *Block,
+ IN UINTN Units
)
{
- UINTN Byte;
- UINT8 Bit;
- UINTN StartByte;
- UINT8 StartBit;
- UINTN Available;
- UINTN Count;
+ UINTN Byte;
+ UINT8 Bit;
+ UINTN StartByte;
+ UINT8 StartBit;
+ UINTN Available;
+ UINTN Count;
ASSERT ((Block != 0) && (Units != 0));
- StartByte = 0;
- StartBit = 0;
- Available = 0;
+ StartByte = 0;
+ StartBit = 0;
+ Available = 0;
for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
//
@@ -164,13 +166,12 @@ UsbHcAllocMemFromBlock ( }
NEXT_BIT (Byte, Bit);
-
} else {
NEXT_BIT (Byte, Bit);
- Available = 0;
- StartByte = Byte;
- StartBit = Bit;
+ Available = 0;
+ StartByte = Byte;
+ StartBit = Bit;
}
}
@@ -181,13 +182,13 @@ UsbHcAllocMemFromBlock ( //
// Mark the memory as allocated
//
- Byte = StartByte;
- Bit = StartBit;
+ Byte = StartByte;
+ Bit = StartBit;
for (Count = 0; Count < Units; Count++) {
ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | (UINT8) USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] | (UINT8)USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -205,16 +206,16 @@ UsbHcAllocMemFromBlock ( **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINTN AllocSize;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINTN Offset;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINTN AllocSize;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINTN Offset;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -228,7 +229,7 @@ UsbHcGetPciAddressForHostMem ( // scan the memory block list for the memory block that
// completely contains the allocated memory.
//
- if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
+ if ((Block->BufHost <= (UINT8 *)Mem) && (((UINT8 *)Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) {
break;
}
}
@@ -237,8 +238,8 @@ UsbHcGetPciAddressForHostMem ( //
// calculate the pci memory address for host memory address.
//
- Offset = (UINT8 *)Mem - Block->BufHost;
- PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset);
+ Offset = (UINT8 *)Mem - Block->BufHost;
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN)(Block->Buf + Offset);
return PhyAddr;
}
@@ -251,8 +252,8 @@ UsbHcGetPciAddressForHostMem ( **/
VOID
UsbHcInsertMemBlockToPool (
- IN USBHC_MEM_BLOCK *Head,
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Head,
+ IN USBHC_MEM_BLOCK *Block
)
{
ASSERT ((Head != NULL) && (Block != NULL));
@@ -271,11 +272,10 @@ UsbHcInsertMemBlockToPool ( **/
BOOLEAN
UsbHcIsMemBlockEmpty (
- IN USBHC_MEM_BLOCK *Block
+ IN USBHC_MEM_BLOCK *Block
)
{
- UINTN Index;
-
+ UINTN Index;
for (Index = 0; Index < Block->BitsLen; Index++) {
if (Block->Bits[Index] != 0) {
@@ -286,7 +286,6 @@ UsbHcIsMemBlockEmpty ( return TRUE;
}
-
/**
Initialize the memory management pool for the host controller.
@@ -301,29 +300,30 @@ UsbHcIsMemBlockEmpty ( **/
USBHC_MEM_POOL *
UsbHcInitMemPool (
- IN PEI_USB2_HC_DEV *Ehc,
- IN BOOLEAN Check4G,
- IN UINT32 Which4G
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN BOOLEAN Check4G,
+ IN UINT32 Which4G
)
{
- USBHC_MEM_POOL *Pool;
- UINTN PageNumber;
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS TempPtr;
-
- PageNumber = sizeof(USBHC_MEM_POOL)/PAGESIZE +1;
- Status = PeiServicesAllocatePages (
- EfiBootServicesCode,
- PageNumber,
- &TempPtr
- );
+ USBHC_MEM_POOL *Pool;
+ UINTN PageNumber;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS TempPtr;
+
+ PageNumber = sizeof (USBHC_MEM_POOL)/PAGESIZE +1;
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesCode,
+ PageNumber,
+ &TempPtr
+ );
+
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
- if (EFI_ERROR (Status)) {
- return NULL;
- }
ZeroMem ((VOID *)(UINTN)TempPtr, PageNumber*EFI_PAGE_SIZE);
- Pool = (USBHC_MEM_POOL *) ((UINTN) TempPtr);
+ Pool = (USBHC_MEM_POOL *)((UINTN)TempPtr);
Pool->Check4G = Check4G;
Pool->Which4G = Which4G;
@@ -348,11 +348,11 @@ UsbHcInitMemPool ( **/
EFI_STATUS
UsbHcFreeMemPool (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool
)
{
- USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *Block;
ASSERT (Pool->Head != NULL);
@@ -381,17 +381,17 @@ UsbHcFreeMemPool ( **/
VOID *
UsbHcAllocateMem (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- USBHC_MEM_BLOCK *NewBlock;
- VOID *Mem;
- UINTN AllocSize;
- UINTN Pages;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ USBHC_MEM_BLOCK *NewBlock;
+ VOID *Mem;
+ UINTN AllocSize;
+ UINTN Pages;
Mem = NULL;
AllocSize = USBHC_MEM_ROUND (Size);
@@ -425,7 +425,8 @@ UsbHcAllocateMem ( } else {
Pages = USBHC_MEM_DEFAULT_PAGES;
}
- NewBlock = UsbHcAllocMemBlock (Ehc,Pool, Pages);
+
+ NewBlock = UsbHcAllocMemBlock (Ehc, Pool, Pages);
if (NewBlock == NULL) {
return NULL;
@@ -455,23 +456,23 @@ UsbHcAllocateMem ( **/
VOID
UsbHcFreeMem (
- IN PEI_USB2_HC_DEV *Ehc,
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
{
- USBHC_MEM_BLOCK *Head;
- USBHC_MEM_BLOCK *Block;
- UINT8 *ToFree;
- UINTN AllocSize;
- UINTN Byte;
- UINTN Bit;
- UINTN Count;
+ USBHC_MEM_BLOCK *Head;
+ USBHC_MEM_BLOCK *Block;
+ UINT8 *ToFree;
+ UINTN AllocSize;
+ UINTN Byte;
+ UINTN Bit;
+ UINTN Count;
Head = Pool->Head;
AllocSize = USBHC_MEM_ROUND (Size);
- ToFree = (UINT8 *) Mem;
+ ToFree = (UINT8 *)Mem;
for (Block = Head; Block != NULL; Block = Block->Next) {
//
@@ -482,8 +483,8 @@ UsbHcFreeMem ( //
// compute the start byte and bit in the bit array
//
- Byte = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) / 8;
- Bit = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) % 8;
+ Byte = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) / 8;
+ Bit = ((ToFree - Block->Buf) / USBHC_MEM_UNIT) % 8;
//
// reset associated bits in bit array
@@ -491,7 +492,7 @@ UsbHcFreeMem ( for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) {
ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit));
- Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit));
+ Block->Bits[Byte] = (UINT8)(Block->Bits[Byte] ^ USB_HC_BIT (Bit));
NEXT_BIT (Byte, Bit);
}
@@ -513,5 +514,5 @@ UsbHcFreeMem ( UsbHcFreeMemBlock (Ehc, Pool, Block);
}
- return ;
+ return;
}
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.h b/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.h index 21b2d7f..7151dbc 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.h +++ b/MdeModulePkg/Bus/Pci/EhciPei/UsbHcMem.h @@ -13,7 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Uefi.h>
#include <IndustryStandard/Pci22.h>
-#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
+#define USB_HC_BIT(a) ((UINTN)(1 << (a)))
#define USB_HC_BIT_IS_SET(Data, Bit) \
((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))
@@ -24,13 +24,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
struct _USBHC_MEM_BLOCK {
- UINT8 *Bits; // Bit array to record which unit is allocated
- UINTN BitsLen;
- UINT8 *Buf;
- UINT8 *BufHost;
- UINTN BufLen; // Memory size in bytes
- VOID *Mapping;
- USBHC_MEM_BLOCK *Next;
+ UINT8 *Bits; // Bit array to record which unit is allocated
+ UINTN BitsLen;
+ UINT8 *Buf;
+ UINT8 *BufHost;
+ UINTN BufLen; // Memory size in bytes
+ VOID *Mapping;
+ USBHC_MEM_BLOCK *Next;
};
//
@@ -39,15 +39,15 @@ struct _USBHC_MEM_BLOCK { // data to be on the same 4G memory.
//
typedef struct _USBHC_MEM_POOL {
- BOOLEAN Check4G;
- UINT32 Which4G;
- USBHC_MEM_BLOCK *Head;
+ BOOLEAN Check4G;
+ UINT32 Which4G;
+ USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
//
// Memory allocation unit, must be 2^n, n>4
//
-#define USBHC_MEM_UNIT 64
+#define USBHC_MEM_UNIT 64
#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
#define USBHC_MEM_DEFAULT_PAGES 16
@@ -66,7 +66,6 @@ typedef struct _USBHC_MEM_POOL { } \
} while (0)
-
/**
Calculate the corresponding pci bus address according to the Mem parameter.
@@ -78,9 +77,9 @@ typedef struct _USBHC_MEM_POOL { **/
EFI_PHYSICAL_ADDRESS
UsbHcGetPciAddressForHostMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
);
#endif
|