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-rw-r--r--EdkModulePkg/Bus/Pci/PciBus/Dxe/PciCommand.h41
-rw-r--r--EdkModulePkg/Bus/Pci/PciBus/Dxe/PciDeviceSupport.c9
-rw-r--r--EdkModulePkg/Bus/Pci/PciBus/Dxe/PciEnumeratorSupport.c17
-rw-r--r--EdkModulePkg/Bus/Pci/PciBus/Dxe/PciIo.c39
-rw-r--r--EdkModulePkg/Bus/Pci/PciBus/Dxe/PciOptionRomSupport.c20
5 files changed, 106 insertions, 20 deletions
diff --git a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciCommand.h b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciCommand.h
index 56f632e..e63d0d1 100644
--- a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciCommand.h
+++ b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciCommand.h
@@ -24,6 +24,47 @@ Revision History
#ifndef _EFI_PCI_COMMAND_H
#define _EFI_PCI_COMMAND_H
+//
+// The PCI Command register bits owned by PCI Bus driver.
+//
+// They should be cleared at the beginning. The other registers
+// are owned by chipset, we should not touch them.
+//
+#define EFI_PCI_COMMAND_BITS_OWNED ( \
+ EFI_PCI_COMMAND_IO_SPACE | \
+ EFI_PCI_COMMAND_MEMORY_SPACE | \
+ EFI_PCI_COMMAND_BUS_MASTER | \
+ EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \
+ EFI_PCI_COMMAND_VGA_PALETTE_SNOOP | \
+ EFI_PCI_COMMAND_FAST_BACK_TO_BACK \
+ )
+
+//
+// The PCI Bridge Control register bits owned by PCI Bus driver.
+//
+// They should be cleared at the beginning. The other registers
+// are owned by chipset, we should not touch them.
+//
+#define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \
+ EFI_PCI_BRIDGE_CONTROL_ISA | \
+ EFI_PCI_BRIDGE_CONTROL_VGA | \
+ EFI_PCI_BRIDGE_CONTROL_VGA_16 | \
+ EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \
+ )
+
+//
+// The PCCard Bridge Control register bits owned by PCI Bus driver.
+//
+// They should be cleared at the beginning. The other registers
+// are owned by chipset, we should not touch them.
+//
+#define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \
+ EFI_PCI_BRIDGE_CONTROL_ISA | \
+ EFI_PCI_BRIDGE_CONTROL_VGA | \
+ EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \
+ )
+
+
#define EFI_GET_REGISTER 1
#define EFI_SET_REGISTER 2
#define EFI_ENABLE_REGISTER 3
diff --git a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciDeviceSupport.c b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciDeviceSupport.c
index 54a7fe7..77e7cba 100644
--- a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciDeviceSupport.c
+++ b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciDeviceSupport.c
@@ -305,6 +305,7 @@ Returns:
UINTN PlatformOpRomSize;
UINT8 PciExpressCapRegOffset;
EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT8 Data8;
//
// Install the pciio protocol, device path protocol
@@ -339,7 +340,8 @@ Returns:
// Force Interrupt line to zero for cards that come up randomly
//
PciIo = &(PciIoDevice->PciIo);
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
+ Data8 = 0xFF;
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
//
// Process Platform OpRom
//
@@ -1149,7 +1151,10 @@ Returns:
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (IS_PCI_VGA(&Temp->Pci) &&
- (Temp->Attributes & (EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_IO))) {
+ (Temp->Attributes &
+ (EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY |
+ EFI_PCI_IO_ATTRIBUTE_VGA_IO |
+ EFI_PCI_IO_ATTRIBUTE_VGA_IO_16))) {
return Temp;
}
diff --git a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciEnumeratorSupport.c b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciEnumeratorSupport.c
index 80bc7d4..ce605cc 100644
--- a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciEnumeratorSupport.c
+++ b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciEnumeratorSupport.c
@@ -394,7 +394,7 @@ Returns:
//
if (gFullEnumeration) {
- PciSetCommandRegister (PciIoDevice, 0);
+ PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
}
@@ -462,12 +462,12 @@ Returns:
);
if (gFullEnumeration) {
- PciSetCommandRegister (PciIoDevice, 0);
+ PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
//
// Initalize the bridge control register
//
- PciSetBridgeControlRegister (PciIoDevice, 0);
+ PciDisableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);
}
@@ -586,12 +586,12 @@ Returns:
);
if (gFullEnumeration) {
- PciSetCommandRegister (PciIoDevice, 0);
+ PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
//
// Initalize the bridge control register
//
- PciSetBridgeControlRegister (PciIoDevice, 0);
+ PciDisableBridgeControlRegister (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);
}
//
@@ -871,6 +871,11 @@ Returns:
Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
}
+ if (BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16) {
+ Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16;
+ Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16;
+ }
+
if (Option == EFI_SET_SUPPORTS) {
Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |
@@ -1066,7 +1071,7 @@ Returns:
EFI_PCI_COMMAND_BUS_MASTER |
EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
- BridgeControl = EFI_PCI_BRIDGE_CONTROL_ISA | EFI_PCI_BRIDGE_CONTROL_VGA;
+ BridgeControl = EFI_PCI_BRIDGE_CONTROL_ISA | EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16;
//
// Test whether the device can support attributes above
diff --git a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciIo.c b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciIo.c
index 28fbaca..e01d6aa 100644
--- a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciIo.c
+++ b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciIo.c
@@ -369,7 +369,7 @@ Returns:
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
- if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
+ if (Width < 0 || Width > EfiPciIoWidthUint64) {
return EFI_INVALID_PARAMETER;
}
@@ -378,10 +378,6 @@ Returns:
return EFI_UNSUPPORTED;
}
- if (Width > EfiPciIoWidthUint64) {
- return EFI_INVALID_PARAMETER;
- }
-
Status = PciIoDevice->PciRootBridgeIo->PollIo (
PciIoDevice->PciRootBridgeIo,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
@@ -1510,11 +1506,25 @@ Returns:
BridgeControl = 0;
//
+ // Check VGA and VGA16, they can not be set at the same time
+ //
+ if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) &&
+ (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) ||
+ ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) &&
+ (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) ||
+ ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) &&
+ (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) ||
+ ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) &&
+ (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) ) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
// For PPB & P2C, set relevant attribute bits
//
if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
- if (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) {
+ if (Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) {
BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA;
}
@@ -1522,18 +1532,23 @@ Returns:
BridgeControl |= EFI_PCI_BRIDGE_CONTROL_ISA;
}
- if (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) {
+ if (Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) {
Command |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
}
+ if (Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) {
+ BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA_16;
+ }
+
} else {
//
// Do with the attributes on VGA
+ // Only for VGA's legacy resource, we just can enable once.
//
- if ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) ||
- (IS_PCI_VGA(&PciIoDevice->Pci) &&
- ((Attributes & EFI_PCI_IO_ATTRIBUTE_IO) ||
- (Attributes & EFI_PCI_IO_ATTRIBUTE_MEMORY)))) {
+ if (Attributes &
+ (EFI_PCI_IO_ATTRIBUTE_VGA_IO |
+ EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |
+ EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) {
//
// Check if a VGA has been enabled before enabling a new one
//
@@ -1554,7 +1569,7 @@ Returns:
//
// Do with the attributes on GFX
//
- if (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) {
+ if (Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) {
if (Operation == EfiPciIoAttributeOperationEnable) {
//
diff --git a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciOptionRomSupport.c b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciOptionRomSupport.c
index 5819fd6..3ec7698 100644
--- a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciOptionRomSupport.c
+++ b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciOptionRomSupport.c
@@ -24,6 +24,13 @@ Revision History
#include "pcibus.h"
#include "PciResourceSupport.h"
+//
+// Min Max
+//
+#define EFI_MIN(a, b) (((a) < (b)) ? (a) : (b))
+#define EFI_MAX(a, b) (((a) > (b)) ? (a) : (b))
+
+
EFI_STATUS
GetOpRomInfo (
IN PCI_IO_DEVICE *PciIoDevice
@@ -152,6 +159,7 @@ Returns:
UINT64 RomSize;
UINT64 RomImageSize;
UINT8 *RomInMemory;
+ UINT8 CodeType;
RomSize = PciDevice->RomSize;
@@ -159,6 +167,7 @@ Returns:
RomImageSize = 0;
RomInMemory = NULL;
Temp = 0;
+ CodeType = 0xFF;
//
// Get the RomBarIndex
@@ -231,11 +240,22 @@ Returns:
sizeof (PCI_DATA_STRUCTURE),
(UINT8 *) RomPcir
);
+ if (RomPcir->CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {
+ CodeType = PCI_CODE_TYPE_PCAT_IMAGE;
+ }
Indicator = RomPcir->Indicator;
RomImageSize = RomImageSize + RomPcir->ImageLength * 512;
RomBarOffset = RomBarOffset + RomPcir->ImageLength * 512;
} while (((Indicator & 0x80) == 0x00) && ((RomBarOffset - RomBar) < RomSize));
+ //
+ // Some Legacy Cards do not report the correct ImageLength so used the maximum
+ // of the legacy length and the PCIR Image Length
+ //
+ if (CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {
+ RomImageSize = EFI_MAX(RomImageSize, (((EFI_LEGACY_EXPANSION_ROM_HEADER *)RomHeader)->Size512 * 512));
+ }
+
if (RomImageSize > 0) {
retStatus = EFI_SUCCESS;
Image = AllocatePool ((UINT32) RomImageSize);
generated by cgit v1.1 at 2024-10-09 23:28:24 +0000