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-rw-r--r--ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc5
-rw-r--r--ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc8
-rw-r--r--ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc7
-rwxr-xr-xArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c6
-rwxr-xr-xArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf2
-rw-r--r--ArmPlatformPkg/PrePeiCore/MainMPCore.c12
-rw-r--r--ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf2
-rw-r--r--ArmPlatformPkg/PrePi/MainMPCore.c10
-rwxr-xr-xArmPlatformPkg/PrePi/PeiMPCore.inf2
-rw-r--r--ArmPlatformPkg/Sec/Sec.c18
-rw-r--r--ArmPlatformPkg/Sec/Sec.inf2
11 files changed, 38 insertions, 36 deletions
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
index a82e13f..12f2cbb 100644
--- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
+++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
@@ -136,7 +136,7 @@
# L2 Cache Driver
L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure
- PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
!if $(EDK2_SKIP_PEICORE) == 1
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
@@ -441,13 +441,14 @@
!if $(EDK2_SKIP_PEICORE) == 1
ArmPlatformPkg/PrePi/PeiUniCore.inf {
<LibraryClasses>
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
}
!else
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf {
<LibraryClasses>
- PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
}
MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
index 5283b45..1852552 100644
--- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
+++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
@@ -115,7 +115,8 @@
# ARM PL011 UART Driver
PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure
- PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
+ ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
@@ -138,8 +139,6 @@
# L2 Cache Driver
L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
- # ARM PL390 General Interrupt Driver in Secure
- PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
!if $(EDK2_SKIP_PEICORE) == 1
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
@@ -451,13 +450,14 @@
!if $(EDK2_SKIP_PEICORE) == 1
ArmPlatformPkg/PrePi/PeiMPCore.inf {
<LibraryClasses>
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
}
!else
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
<LibraryClasses>
- PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
}
MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
index ed1c616..d4be10b 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
@@ -147,8 +147,8 @@
#DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure
- PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
- PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
+ ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
!if $(EDK2_SKIP_PEICORE) == 1
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
@@ -496,13 +496,14 @@
!if $(EDK2_SKIP_PEICORE) == 1
ArmPlatformPkg/PrePi/PeiMPCore.inf {
<LibraryClasses>
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
}
!else
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
<LibraryClasses>
- PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
}
MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
diff --git a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
index 469a545..b981214 100755
--- a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
+++ b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
@@ -14,12 +14,12 @@
#include <PiPei.h>
+#include <Library/ArmGicLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
#include <Chipset/ArmV7.h>
-#include <Drivers/PL390Gic.h>
#define ARM_PRIMARY_CORE 0
@@ -38,7 +38,7 @@ NonSecureWaitForFirmware (
ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal.
- PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
// Jump to secondary core entry point.
secondary_start ();
@@ -87,7 +87,7 @@ ArmPlatformSecExtraAction (
} else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
if (CoreId == ARM_PRIMARY_CORE) {
// Signal the secondary cores they can jump to PEI phase
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
// To enter into Non Secure state, we need to make a return from exception
*JumpAddress = PcdGet32(PcdNormalFvBaseAddress);
diff --git a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
index 4b5df28..2a09063 100755
--- a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+++ b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
@@ -36,7 +36,7 @@
[LibraryClasses]
DebugLib
PcdLib
- PL390GicSecLib
+ ArmGicSecLib
PrintLib
SerialPortLib
diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index 35c4154..a369c6e 100644
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -12,9 +12,9 @@
*
**/
+#include <Library/ArmGicLib.h>
#include <Library/ArmMPCoreMailBoxLib.h>
#include <Chipset/ArmV7.h>
-#include <Drivers/PL390Gic.h>
#include "PrePeiCore.h"
@@ -45,7 +45,7 @@ SecondaryMain (
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal.
- PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
+ ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
}
secondary_start = (VOID (*)())secondary_entry_addr;
@@ -65,13 +65,13 @@ PrimaryMain (
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
- //Enable the GIC Distributor
- PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
+ // Enable the GIC Distributor
+ ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores
- if (FeaturePcdGet(PcdSendSgiToBringUpSecondaryCores)) {
+ if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
// Sending SGI to all the Secondary CPU interfaces
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
}
//
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
index 8c25544..c2506ab 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
@@ -44,7 +44,7 @@
DebugLib
DebugAgentLib
IoLib
- PL390GicNonSecLib
+ ArmGicLib
PrintLib
SerialPortLib
diff --git a/ArmPlatformPkg/PrePi/MainMPCore.c b/ArmPlatformPkg/PrePi/MainMPCore.c
index 165e7cf..82d3190 100644
--- a/ArmPlatformPkg/PrePi/MainMPCore.c
+++ b/ArmPlatformPkg/PrePi/MainMPCore.c
@@ -14,9 +14,9 @@
#include "PrePi.h"
+#include <Library/ArmGicLib.h>
#include <Library/ArmMPCoreMailBoxLib.h>
#include <Chipset/ArmV7.h>
-#include <Drivers/PL390Gic.h>
VOID
PrimaryMain (
@@ -24,13 +24,13 @@ PrimaryMain (
IN UINT64 StartTimeStamp
)
{
- //Enable the GIC Distributor
- PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
+ // Enable the GIC Distributor
+ ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
// In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization
if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {
// Sending SGI to all the Secondary CPU interfaces
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
}
PrePiMain (UefiMemoryBase, StartTimeStamp);
@@ -54,7 +54,7 @@ SecondaryMain (
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal.
- PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
+ ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
}
secondary_start = (VOID (*)())secondary_entry_addr;
diff --git a/ArmPlatformPkg/PrePi/PeiMPCore.inf b/ArmPlatformPkg/PrePi/PeiMPCore.inf
index 3978118..c8af14d 100755
--- a/ArmPlatformPkg/PrePi/PeiMPCore.inf
+++ b/ArmPlatformPkg/PrePi/PeiMPCore.inf
@@ -40,7 +40,7 @@
DebugAgentLib
ArmLib
ArmMPCoreMailBoxLib
- PL390GicNonSecLib
+ ArmGicLib
IoLib
TimerLib
SerialPortLib
diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index 42df66e..5610168 100644
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -24,7 +24,7 @@
#include <Library/ArmPlatformLib.h>
#include <Chipset/ArmV7.h>
-#include <Drivers/PL390Gic.h>
+#include <Library/ArmGicLib.h>
#define ARM_PRIMARY_CORE 0
@@ -160,27 +160,27 @@ CEntryPoint (
// 3: As all the cores are in secure state, use secure SGI's
//
- PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
- PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Send SGI to all Secondary core to wake them up from WFI state.
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
} else {
// The secondary cores need to wait until the Trustzone chipsets configuration is done
// before switching to Non Secure World
// Enabled GIC CPU Interface
- PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Waiting for the SGI from the primary core
ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal.
- PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
}
// Transfer the interrupt to Non-secure World
- PL390GicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
// Write to CP15 Non-secure Access Control Register :
// - Enable CP10 and CP11 accesses in NS World
@@ -199,9 +199,9 @@ CEntryPoint (
// Trustzone is not enabled, just enable the Distributor and CPU interface
if (CoreId == ARM_PRIMARY_CORE) {
- PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+ ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
}
- PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf
index 23dee11..bffa9b6 100644
--- a/ArmPlatformPkg/Sec/Sec.inf
+++ b/ArmPlatformPkg/Sec/Sec.inf
@@ -42,7 +42,7 @@
DebugLib
DebugAgentLib
IoLib
- PL390GicSecLib
+ ArmGicSecLib
PrintLib
SerialPortLib
generated by cgit v1.1 at 2024-11-13 01:29:00 +0000