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-rw-r--r--ArmPlatformPkg/ArmPlatformPkg.dsc1
-rw-r--r--ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c8
-rw-r--r--ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf2
-rw-r--r--ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c2
-rw-r--r--ArmPlatformPkg/PeilessSec/AArch64/ModuleEntryPoint.S20
-rw-r--r--ArmPlatformPkg/PeilessSec/PeilessSec.c31
-rw-r--r--ArmPlatformPkg/PeilessSec/PeilessSec.h2
-rw-r--r--ArmPlatformPkg/PeilessSec/PeilessSec.inf2
-rw-r--r--ArmPlatformPkg/PlatformPei/PlatformPeim.c21
-rw-r--r--ArmPlatformPkg/PlatformPei/PlatformPeim.inf4
-rw-r--r--ArmPlatformPkg/Sec/AArch64/ModuleEntryPoint.S16
-rw-r--r--ArmPlatformPkg/Sec/Sec.c48
-rw-r--r--ArmPlatformPkg/Sec/Sec.h1
-rw-r--r--ArmPlatformPkg/Sec/Sec.inf2
14 files changed, 140 insertions, 20 deletions
diff --git a/ArmPlatformPkg/ArmPlatformPkg.dsc b/ArmPlatformPkg/ArmPlatformPkg.dsc
index 062246d..278d3cf 100644
--- a/ArmPlatformPkg/ArmPlatformPkg.dsc
+++ b/ArmPlatformPkg/ArmPlatformPkg.dsc
@@ -70,6 +70,7 @@
UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ ArmTransferListLib|ArmPkg/Library/ArmTransferListLib/ArmTransferListLib.inf
[LibraryClasses.common.PEIM]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
diff --git a/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c b/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c
index bf437af..afa3fc4 100644
--- a/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c
+++ b/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c
@@ -37,11 +37,11 @@ SerialPortInitialize (
EFI_STATUS Status;
UINT8 Scratch;
- BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
+ BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
ReceiveFifoDepth = 0; // Use default FIFO depth
- Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
- DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
- StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits);
+ Parity = (EFI_PARITY_TYPE)PcdGet8 (PcdUartDefaultParity);
+ DataBits = PcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE)PcdGet8 (PcdUartDefaultStopBits);
Status = PL011UartInitializePort (
(UINTN)PcdGet64 (PcdSerialRegisterBase),
diff --git a/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf b/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
index b6b87f3..07424cc 100644
--- a/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+++ b/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
@@ -33,7 +33,7 @@
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
-[FixedPcd]
+[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c
index 60f9bc5..e8e2e1d 100644
--- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c
+++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c
@@ -193,7 +193,7 @@ PL011UartInitializePort (
return RETURN_INVALID_PARAMETER;
}
- Divisor = (UartClkInHz * 4) / *BaudRate;
+ Divisor = (UINT32)((UartClkInHz * 4) / *BaudRate);
Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;
Fractional = Divisor & FRACTION_PART_MASK;
}
diff --git a/ArmPlatformPkg/PeilessSec/AArch64/ModuleEntryPoint.S b/ArmPlatformPkg/PeilessSec/AArch64/ModuleEntryPoint.S
index 5f285f3..94635ef 100644
--- a/ArmPlatformPkg/PeilessSec/AArch64/ModuleEntryPoint.S
+++ b/ArmPlatformPkg/PeilessSec/AArch64/ModuleEntryPoint.S
@@ -1,13 +1,29 @@
//
-// Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>
+// Copyright (c) 2011 - 2025, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
+// @Par Reference(s):
+// - Firmware Handoff specification [https://firmwarehandoff.github.io/firmware_handoff/main]
//
#include <AsmMacroLib.h>
ASM_FUNC(_ModuleEntryPoint)
+
+ // Check if register assignment at handoff matches spec
+ MOV64 (x4, 0x14a0fb10b)
+ cmp x1, x4
+ // Skip TransferList init if x1 is not equal to the TransferList signature
+ b.ne _SkipTransferList
+
+ // Skip TransferList init if x2 is not equal to 0
+ cbnz x2, _SkipTransferList
+
+ // Set the TransferList Base Address from register x3
+ mov x6, x3
+
+_SkipTransferList:
// Do early platform specific actions
bl ASM_PFX(ArmPlatformPeiBootAction)
@@ -76,6 +92,8 @@ _GetStackBase:
MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
sub x1, x1, x2
+ // Pass Transfer List Base Address
+ mov x2, x6
// Move sec startup address into a data register
// Ensure we're jumping to FV version of the code (not boot remapped alias)
ldr x4, =ASM_PFX(CEntryPoint)
diff --git a/ArmPlatformPkg/PeilessSec/PeilessSec.c b/ArmPlatformPkg/PeilessSec/PeilessSec.c
index 639c374..b9b7196 100644
--- a/ArmPlatformPkg/PeilessSec/PeilessSec.c
+++ b/ArmPlatformPkg/PeilessSec/PeilessSec.c
@@ -53,13 +53,15 @@ GetPlatformPpi (
@param[in] UefiMemoryBase Start of the PI/UEFI memory region
@param[in] StackBase Start of the stack
@param[in] StartTimeStamp Timer value at start of execution
+ @param[in] TransferListBaseAddr Base address of the Transfer List
**/
STATIC
VOID
SecMain (
IN UINTN UefiMemoryBase,
IN UINTN StackBase,
- IN UINT64 StartTimeStamp
+ IN UINT64 StartTimeStamp,
+ IN UINTN TransferListBaseAddr
)
{
EFI_HOB_HANDOFF_INFO_TABLE *HobList;
@@ -71,6 +73,8 @@ SecMain (
UINTN CharCount;
UINTN StacksSize;
FIRMWARE_SEC_PERFORMANCE Performance;
+ VOID *TransferListBase;
+ UINTN *TransferListHobData;
// If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)
ASSERT (
@@ -134,6 +138,25 @@ SecMain (
}
}
+ // Dump the Transfer List
+ TransferListBase = (VOID *)TransferListBaseAddr;
+ if (TransferListBase != NULL) {
+ if (TransferListCheckHeader (TransferListBase) != TRANSFER_LIST_OPS_INVALID) {
+ DEBUG_CODE_BEGIN ();
+ TransferListDump (TransferListBase);
+ DEBUG_CODE_END ();
+
+ TransferListHobData = BuildGuidHob (&gArmTransferListHobGuid, sizeof (*TransferListHobData));
+ ASSERT (TransferListHobData != NULL);
+
+ *TransferListHobData = (UINTN)TransferListBase;
+ } else {
+ DEBUG ((DEBUG_ERROR, "%a: No valid operations possible on TransferList found @ 0x%p\n", __func__, TransferListBase));
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "%a: No TransferList found, continuing boot\n", __func__));
+ }
+
// Store timer value logged at the beginning of firmware image execution
Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);
@@ -167,11 +190,13 @@ SecMain (
@param[in] UefiMemoryBase Start of the PI/UEFI memory region
@param[in] StackBase Start of the stack
+ @param[in] TransferListBaseAddr Base address of the Transfer List
**/
VOID
CEntryPoint (
IN UINTN UefiMemoryBase,
- IN UINTN StackBase
+ IN UINTN StackBase,
+ IN UINTN TransferListBaseAddr
)
{
UINT64 StartTimeStamp;
@@ -198,7 +223,7 @@ CEntryPoint (
FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)
);
- SecMain (UefiMemoryBase, StackBase, StartTimeStamp);
+ SecMain (UefiMemoryBase, StackBase, StartTimeStamp, TransferListBaseAddr);
// DXE Core should always load and never return
ASSERT (FALSE);
diff --git a/ArmPlatformPkg/PeilessSec/PeilessSec.h b/ArmPlatformPkg/PeilessSec/PeilessSec.h
index 70d78ca..73b6b25 100644
--- a/ArmPlatformPkg/PeilessSec/PeilessSec.h
+++ b/ArmPlatformPkg/PeilessSec/PeilessSec.h
@@ -24,6 +24,8 @@
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
#include <Library/TimerLib.h>
+#include <Library/ArmTransferListLib.h>
+#include <Guid/TransferListHob.h>
#include <Ppi/ArmMpCoreInfo.h>
#include <Ppi/GuidedSectionExtraction.h>
diff --git a/ArmPlatformPkg/PeilessSec/PeilessSec.inf b/ArmPlatformPkg/PeilessSec/PeilessSec.inf
index e210d01..db7449f 100644
--- a/ArmPlatformPkg/PeilessSec/PeilessSec.inf
+++ b/ArmPlatformPkg/PeilessSec/PeilessSec.inf
@@ -52,6 +52,7 @@
SerialPortLib
TimerLib
StackCheckLib
+ ArmTransferListLib
[Ppis]
gArmMpCoreInfoPpiGuid
@@ -59,6 +60,7 @@
[Guids]
gArmMpCoreInfoGuid
gEfiFirmwarePerformanceGuid
+ gArmTransferListHobGuid
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
diff --git a/ArmPlatformPkg/PlatformPei/PlatformPeim.c b/ArmPlatformPkg/PlatformPei/PlatformPeim.c
index 62d1faf..921371a 100644
--- a/ArmPlatformPkg/PlatformPei/PlatformPeim.c
+++ b/ArmPlatformPkg/PlatformPei/PlatformPeim.c
@@ -24,6 +24,7 @@
#include <Library/PeimEntryPoint.h>
#include <Library/PeiServicesLib.h>
#include <Library/PcdLib.h>
+#include <Guid/TransferListHob.h>
EFI_STATUS
EFIAPI
@@ -76,14 +77,30 @@ InitializePlatformPeim (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- EFI_STATUS Status;
- EFI_BOOT_MODE BootMode;
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ VOID *TransferListBase;
+ UINTN *TransferListHobData;
+ EFI_HOB_GUID_TYPE *GuidHob;
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Platform PEIM Loaded\n"));
Status = PeiServicesSetBootMode (ArmPlatformGetBootMode ());
ASSERT_EFI_ERROR (Status);
+ // If TransferList PPI is present and TransferListHobGuid is not present,
+ // then create a TransferListHob with the TransferListBase address.
+ Status = PeiServicesLocatePpi (&gArmTransferListPpiGuid, 0, NULL, &TransferListBase);
+ if (!EFI_ERROR (Status)) {
+ GuidHob = GetFirstGuidHob (&gArmTransferListHobGuid);
+ if ((GuidHob == NULL) && (TransferListBase != NULL)) {
+ TransferListHobData = BuildGuidHob (&gArmTransferListHobGuid, sizeof (*TransferListHobData));
+ ASSERT (TransferListHobData != NULL);
+
+ *TransferListHobData = (UINTN)TransferListBase;
+ }
+ }
+
PlatformPeim ();
Status = PeiServicesGetBootMode (&BootMode);
diff --git a/ArmPlatformPkg/PlatformPei/PlatformPeim.inf b/ArmPlatformPkg/PlatformPei/PlatformPeim.inf
index f2b0e0f..d9e8f32 100644
--- a/ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+++ b/ArmPlatformPkg/PlatformPei/PlatformPeim.inf
@@ -43,6 +43,7 @@
[Ppis]
gEfiPeiMasterBootModePpiGuid # PPI ALWAYS_PRODUCED
gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED
+ gArmTransferListPpiGuid # PPI SOMETIMES_CONSUMED
[FixedPcd]
gArmTokenSpaceGuid.PcdFdBaseAddress
@@ -51,6 +52,9 @@
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
+[Guids]
+ gArmTransferListHobGuid
+
[Depex]
TRUE
diff --git a/ArmPlatformPkg/Sec/AArch64/ModuleEntryPoint.S b/ArmPlatformPkg/Sec/AArch64/ModuleEntryPoint.S
index 154be11..28cd015 100644
--- a/ArmPlatformPkg/Sec/AArch64/ModuleEntryPoint.S
+++ b/ArmPlatformPkg/Sec/AArch64/ModuleEntryPoint.S
@@ -8,6 +8,19 @@
#include <AsmMacroLib.h>
ASM_FUNC(_ModuleEntryPoint)
+ // Check if register assignment at handoff matches spec
+ MOV64 (x4, 0x14a0fb10b)
+ // Check if x1 holds TransferList signature
+ cmp x1, x4
+ b.ne _SkipTransferList
+
+ // Skip TransferList init if x2 is not equal to 0
+ cbnz x2, _SkipTransferList
+
+ // Set the TransferList Base Address from register x3
+ mov x10, x3
+
+_SkipTransferList:
// Do early platform specific actions
bl ASM_PFX(ArmPlatformPeiBootAction)
@@ -47,7 +60,8 @@ ASM_PFX(MainEntryPoint):
// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
MOV64 (x2, FixedPcdGet64(PcdFvBaseAddress))
ldr x0, [x2, #8]
-
+ // Pass the TransferList Base Address
+ mov x1, x10
// Move sec startup address into a data register
// Ensure we're jumping to FV version of the code (not boot remapped alias)
ldr x3, =ASM_PFX(CEntryPoint)
diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index 4535ae7..ec8bec2 100644
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -86,12 +86,14 @@ STATIC CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {
@param[out] PpiListSize Size of the PPI list in bytes
@param[out] PpiList Pointer to the constructed PPI list
+ @param[in] TransferListBase Pointer to the Transfer List base
**/
STATIC
VOID
CreatePpiList (
OUT UINTN *PpiListSize,
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList,
+ IN VOID *TransferListBase
)
{
EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;
@@ -111,10 +113,20 @@ CreatePpiList (
// Set the Terminate flag on the last PPI entry
LastPpi = (EFI_PEI_PPI_DESCRIPTOR *)ListBase +
((sizeof (gCommonPpiTable) + PlatformPpiListSize) / sizeof (EFI_PEI_PPI_DESCRIPTOR)) - 1;
+ *PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;
+
+ // Add the Transfer List PPI after the Common and Platform PPIs
+ if (TransferListBase != NULL) {
+ LastPpi++;
+ LastPpi->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI;
+ LastPpi->Guid = &gArmTransferListPpiGuid;
+ LastPpi->Ppi = TransferListBase;
+ *PpiListSize += sizeof (EFI_PEI_PPI_DESCRIPTOR);
+ }
+
LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
- *PpiList = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;
- *PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;
+ *PpiList = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;
}
/**
@@ -151,12 +163,15 @@ PrintFirmwareVersion (
@param[in] PeiCoreEntryPoint Address in ram of the entrypoint of the PEI
core
+ @param[in] TransferListBaseAddr Address of the Transfer List base address
+
**/
STATIC
VOID
EFIAPI
SecMain (
- IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
+ IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint,
+ IN UINTN TransferListBaseAddr
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
@@ -164,8 +179,24 @@ SecMain (
EFI_PEI_PPI_DESCRIPTOR *PpiList;
UINTN TemporaryRamBase;
UINTN TemporaryRamSize;
+ VOID *TransferListBase;
+
+ // Dump the Transfer List
+ TransferListBase = (VOID *)TransferListBaseAddr;
+ if (TransferListBase != NULL) {
+ if (TransferListCheckHeader (TransferListBase) != TRANSFER_LIST_OPS_INVALID) {
+ DEBUG_CODE_BEGIN ();
+ TransferListDump (TransferListBase);
+ DEBUG_CODE_END ();
+ } else {
+ TransferListBase = NULL;
+ DEBUG ((DEBUG_ERROR, "%a: No valid operations possible on TransferList found @ 0x%p\n", __func__, TransferListBase));
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "%a: No TransferList found, continuing boot\n", __func__));
+ }
- CreatePpiList (&PpiListSize, &PpiList);
+ CreatePpiList (&PpiListSize, &PpiList, TransferListBase);
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
// the base of the primary core stack
@@ -197,10 +228,13 @@ SecMain (
@param[in] PeiCoreEntryPoint Address in ram of the entrypoint of the PEI
core
+ @param[in] TransferListBaseAddr Address of the Transfer List base address
+
**/
VOID
CEntryPoint (
- IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
+ IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint,
+ IN UINTN TransferListBaseAddr
)
{
if (!ArmMmuEnabled ()) {
@@ -237,7 +271,7 @@ CEntryPoint (
ArmPlatformInitialize (ArmReadMpidr ());
// Goto primary Main.
- SecMain (PeiCoreEntryPoint);
+ SecMain (PeiCoreEntryPoint, TransferListBaseAddr);
// PEI Core should always load and never return
ASSERT (FALSE);
diff --git a/ArmPlatformPkg/Sec/Sec.h b/ArmPlatformPkg/Sec/Sec.h
index 56d9f35..c1cd10d 100644
--- a/ArmPlatformPkg/Sec/Sec.h
+++ b/ArmPlatformPkg/Sec/Sec.h
@@ -23,6 +23,7 @@
#include <Library/SerialPortLib.h>
#include <Ppi/TemporaryRamSupport.h>
+#include <Library/ArmTransferListLib.h>
/**
Helper function to switch to a different stack. Implemented in assembler as
diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf
index a75ce8d..6206707 100644
--- a/ArmPlatformPkg/Sec/Sec.inf
+++ b/ArmPlatformPkg/Sec/Sec.inf
@@ -48,9 +48,11 @@
PrintLib
SerialPortLib
StackCheckLib
+ ArmTransferListLib
[Ppis]
gEfiTemporaryRamSupportPpiGuid
+ gArmTransferListPpiGuid
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
generated by cgit v1.1 at 2025-08-01 05:49:29 +0000