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-rw-r--r--ArmPlatformPkg/PrePeiCore/MainMPCore.c4
-rw-r--r--ArmPlatformPkg/PrePeiCore/MainUniCore.c2
-rw-r--r--ArmPlatformPkg/PrePeiCore/PrePeiCore.c6
-rw-r--r--ArmPlatformPkg/PrePeiCore/PrePeiCore.h2
-rw-r--r--ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S13
-rw-r--r--ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm9
-rw-r--r--ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf3
7 files changed, 22 insertions, 17 deletions
diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index a369c6e..036b192 100644
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -32,7 +32,7 @@ extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
VOID
EFIAPI
SecondaryMain (
- IN UINTN CoreId
+ IN UINTN MpId
)
{
// Function pointer to Secondary Core entry point
@@ -45,7 +45,7 @@ SecondaryMain (
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal.
- ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
}
secondary_start = (VOID (*)())secondary_entry_addr;
diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c b/ArmPlatformPkg/PrePeiCore/MainUniCore.c
index 4d83312..179e1ea 100644
--- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c
@@ -21,7 +21,7 @@ extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
VOID
EFIAPI
SecondaryMain (
- IN UINTN CoreId
+ IN UINTN MpId
)
{
ASSERT(FALSE);
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index 0b7f973..c557efe 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -36,7 +36,7 @@ EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = {
VOID
CEntryPoint (
- IN UINTN CoreId,
+ IN UINTN MpId,
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
)
{
@@ -62,7 +62,7 @@ CEntryPoint (
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
//If not primary Jump to Secondary Main
- if(0 == CoreId) {
+ if (IS_PRIMARY_CORE(MpId)) {
// Initialize the Debug Agent for Source Level Debugging
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
SaveAndSetDebugTimerInterrupt (TRUE);
@@ -70,7 +70,7 @@ CEntryPoint (
// Goto primary Main.
PrimaryMain (PeiCoreEntryPoint);
} else {
- SecondaryMain (CoreId);
+ SecondaryMain (MpId);
}
// PEI Core should always load and never return
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
index 7a369b4..05198b8 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
@@ -57,7 +57,7 @@ PrimaryMain (
VOID
EFIAPI
SecondaryMain (
- IN UINTN CoreId
+ IN UINTN MpId
);
#endif
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
index 49174cc..01723a2 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
@@ -19,19 +19,18 @@
.text
.align 3
-#global symbols referenced by this module
GCC_ASM_IMPORT(CEntryPoint)
-
-StartupAddr: .word CEntryPoint
-
-#make _ModuleEntryPoint as global
+GCC_ASM_IMPORT(ArmReadMpidr)
GCC_ASM_EXPORT(_ModuleEntryPoint)
+StartupAddr: .word CEntryPoint
ASM_PFX(_ModuleEntryPoint):
# Identify CPU ID
- mrc p15, 0, r0, c0, c0, 5
- and r0, #0xf
+ bl ASM_PFX(ArmReadMpidr)
+ // Get ID of this CPU in Multicore system
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
+ and r0, r0, r1
_SetupStack:
# Setup Stack for the 4 CPU cores
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm
index e214ed3..e4eb612 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm
@@ -19,6 +19,7 @@
INCLUDE AsmMacroIoLib.inc
IMPORT CEntryPoint
+ IMPORT ArmReadMpidr
EXPORT _ModuleEntryPoint
PRESERVE8
@@ -28,8 +29,10 @@ StartupAddr DCD CEntryPoint
_ModuleEntryPoint
// Identify CPU ID
- mrc p15, 0, r0, c0, c0, 5
- and r0, #0xf
+ bl ArmReadMpidr
+ // Get ID of this CPU in Multicore system
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
+ and r0, r0, r1
_SetupStack
// Setup Stack for the 4 CPU cores
@@ -62,7 +65,7 @@ _PrepareArguments
ldr r2, StartupAddr
// jump to PrePeiCore C code
- // r0 = core_id
+ // r0 = mp_id
// r1 = pei_core_address
blx r2
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
index c2506ab..25dae0f 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
@@ -58,6 +58,9 @@
gArmTokenSpaceGuid.PcdNormalFvBaseAddress
gArmTokenSpaceGuid.PcdNormalFvSize
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize