2 files changed, 15 insertions, 2 deletions
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
index 74810ec..aa68af9 100644
--- a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
@@ -343,7 +343,15 @@ InterruptDxeInitialize (
   UINT32                  RegOffset;
   UINTN                   RegShift;
   EFI_CPU_ARCH_PROTOCOL   *Cpu;
+  UINT32                  CpuTarget;
   
+  // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
+  DEBUG_CODE_BEGIN();
+  if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {
+    DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));
+  }
+  DEBUG_CODE_END();
+
   // Make sure the Interrupt Controller Protocol is not already installed in the system.
   ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
 
@@ -362,9 +370,11 @@ InterruptDxeInitialize (
       );
   }
 
-  // Configure interrupts for cpu 0
+  // Configure interrupts for Primary Cpu
+  CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId));
+  CpuTarget |= (CpuTarget << 24) | (CpuTarget << 16) | (CpuTarget << 8);
   for (Index = 0; Index < (mGicNumInterrupts / 4); Index++) {
-    MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), 0x01010101);
+    MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget);
   }
 
   // Set binary point reg to 0x7 (no preemption)
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
index 7239315..b63216e 100644
--- a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
@@ -49,6 +49,9 @@
 [FixedPcd.common]
   gArmTokenSpaceGuid.PcdGicDistributorBase
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gArmTokenSpaceGuid.PcdGicPrimaryCoreId
 
 [Depex]
   gEfiCpuArchProtocolGuid