diff options
Diffstat (limited to 'ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S')
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 166 |
1 files changed, 116 insertions, 50 deletions
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index 991de89..cfbb8f5 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -12,55 +12,51 @@ # #------------------------------------------------------------------------------ -.globl ASM_PFX(ArmInvalidateInstructionCache) -INTERWORK_FUNC(ArmInvalidateInstructionCache) -.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA) -INTERWORK_FUNC(ArmInvalidateDataCacheEntryByMVA) -.globl ASM_PFX(ArmCleanDataCacheEntryByMVA) -INTERWORK_FUNC(ArmCleanDataCacheEntryByMVA) -.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA) -INTERWORK_FUNC(ArmCleanInvalidateDataCacheEntryByMVA) -.globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay) -INTERWORK_FUNC(ArmInvalidateDataCacheEntryBySetWay) -.globl ASM_PFX(ArmCleanDataCacheEntryBySetWay) -INTERWORK_FUNC(ArmCleanDataCacheEntryBySetWay) -.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay) -INTERWORK_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay) -.globl ASM_PFX(ArmDrainWriteBuffer) -INTERWORK_FUNC(ArmDrainWriteBuffer) -.globl ASM_PFX(ArmEnableMmu) -INTERWORK_FUNC(ArmEnableMmu) -.globl ASM_PFX(ArmDisableMmu) -INTERWORK_FUNC(ArmDisableMmu) -.globl ASM_PFX(ArmMmuEnabled) -INTERWORK_FUNC(ArmMmuEnabled) -.globl ASM_PFX(ArmEnableDataCache) -INTERWORK_FUNC(ArmEnableDataCache) -.globl ASM_PFX(ArmDisableDataCache) -INTERWORK_FUNC(ArmDisableDataCache) -.globl ASM_PFX(ArmEnableInstructionCache) -INTERWORK_FUNC(ArmEnableInstructionCache) -.globl ASM_PFX(ArmDisableInstructionCache) -INTERWORK_FUNC(ArmDisableInstructionCache) -.globl ASM_PFX(ArmEnableBranchPrediction) -INTERWORK_FUNC(ArmEnableBranchPrediction) -.globl ASM_PFX(ArmDisableBranchPrediction) -INTERWORK_FUNC(ArmDisableBranchPrediction) -.globl ASM_PFX(ArmV7AllDataCachesOperation) -INTERWORK_FUNC(ArmV7AllDataCachesOperation) -.globl ASM_PFX(ArmDataMemoryBarrier) -INTERWORK_FUNC(ArmDataMemoryBarrier) -.globl ASM_PFX(ArmDataSyncronizationBarrier) -INTERWORK_FUNC(ArmDataSyncronizationBarrier) -.globl ASM_PFX(ArmInstructionSynchronizationBarrier) -INTERWORK_FUNC(ArmInstructionSynchronizationBarrier) - .text .align 2 +GCC_ASM_EXPORT (ArmInvalidateInstructionCache) +GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA) +GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA) +GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA) +GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay) +GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay) +GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay) +GCC_ASM_EXPORT (ArmDrainWriteBuffer) +GCC_ASM_EXPORT (ArmEnableMmu) +GCC_ASM_EXPORT (ArmDisableMmu) +GCC_ASM_EXPORT (ArmDisableCachesAndMmu) +GCC_ASM_EXPORT (ArmMmuEnabled) +GCC_ASM_EXPORT (ArmEnableDataCache) +GCC_ASM_EXPORT (ArmDisableDataCache) +GCC_ASM_EXPORT (ArmEnableInstructionCache) +GCC_ASM_EXPORT (ArmDisableInstructionCache) +GCC_ASM_EXPORT (ArmEnableSWPInstruction) +GCC_ASM_EXPORT (ArmEnableBranchPrediction) +GCC_ASM_EXPORT (ArmDisableBranchPrediction) +GCC_ASM_EXPORT (ArmV7AllDataCachesOperation) +GCC_ASM_EXPORT (ArmDataMemoryBarrier) +GCC_ASM_EXPORT (ArmDataSyncronizationBarrier) +GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier) +GCC_ASM_EXPORT (ArmWriteNsacr) +GCC_ASM_EXPORT (ArmWriteScr) +GCC_ASM_EXPORT (ArmWriteVMBar) +GCC_ASM_EXPORT (ArmWriteVBar) +GCC_ASM_EXPORT (ArmWriteCPACR) +GCC_ASM_EXPORT (ArmEnableVFP) +GCC_ASM_EXPORT (ArmCallWFI) +GCC_ASM_EXPORT (ArmWriteAuxCr) +GCC_ASM_EXPORT (ArmReadAuxCr) +GCC_ASM_EXPORT (ArmReadCbar) +GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb) +GCC_ASM_EXPORT (ArmReadMpidr) + .set DC_ON, (0x1<<2) .set IC_ON, (0x1<<12) - +.set CTRL_M_BIT, (1 << 0) +.set CTRL_C_BIT, (1 << 2) +.set CTRL_B_BIT, (1 << 7) +.set CTRL_I_BIT, (1 << 12) ASM_PFX(ArmInvalidateDataCacheEntryByMVA): @@ -69,7 +65,6 @@ ASM_PFX(ArmInvalidateDataCacheEntryByMVA): isb bx lr - ASM_PFX(ArmCleanDataCacheEntryByMVA): mcr p15, 0, r0, c7, c10, 1 @clean single data cache line dsb @@ -104,7 +99,6 @@ ASM_PFX(ArmCleanDataCacheEntryBySetWay): isb bx lr - ASM_PFX(ArmInvalidateInstructionCache): mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache dsb @@ -119,10 +113,6 @@ ASM_PFX(ArmEnableMmu): isb bx LR -ASM_PFX(ArmMmuEnabled): - mrc p15,0,R0,c1,c0,0 - and R0,R0,#1 - bx LR ASM_PFX(ArmDisableMmu): mrc p15,0,R0,c1,c0,0 @@ -135,6 +125,21 @@ ASM_PFX(ArmDisableMmu): isb bx LR +ASM_PFX(ArmDisableCachesAndMmu): + mrc p15, 0, r0, c1, c0, 0 @ Get control register + bic r0, r0, #CTRL_M_BIT @ Disable MMU + bic r0, r0, #CTRL_C_BIT @ Disable D Cache + bic r0, r0, #CTRL_I_BIT @ Disable I Cache + mcr p15, 0, r0, c1, c0, 0 @ Write control register + dsb + isb + bx LR + +ASM_PFX(ArmMmuEnabled): + mrc p15,0,R0,c1,c0,0 + and R0,R0,#1 + bx LR + ASM_PFX(ArmEnableDataCache): ldr R1,=DC_ON mrc p15,0,R0,c1,c0,0 @Read control register configuration data @@ -171,6 +176,13 @@ ASM_PFX(ArmDisableInstructionCache): isb bx LR +ASM_PFX(ArmEnableSWPInstruction): + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00000400 + mcr p15, 0, r0, c1, c0, 0 + isb + bx LR + ASM_PFX(ArmEnableBranchPrediction): mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #0x00000800 @@ -254,5 +266,59 @@ ASM_PFX(ArmInstructionSynchronizationBarrier): isb bx LR +ASM_PFX(ArmWriteNsacr): + mcr p15, 0, r0, c1, c1, 2 + bx lr + +ASM_PFX(ArmWriteScr): + mcr p15, 0, r0, c1, c1, 0 + bx lr + +ASM_PFX(ArmWriteAuxCr): + mcr p15, 0, r0, c1, c0, 1 + bx lr + +ASM_PFX(ArmReadAuxCr): + mrc p15, 0, r0, c1, c0, 1 + bx lr + +ASM_PFX(ArmWriteVMBar): + mcr p15, 0, r0, c12, c0, 1 + bx lr + +ASM_PFX(ArmWriteVBar): + mcr p15, 0, r0, c12, c0, 0 + bx lr + +ASM_PFX(ArmWriteCPACR): + mcr p15, 0, r0, c1, c0, 2 + bx lr + +ASM_PFX(ArmEnableVFP): + // Enable VFP registers + mrc p15, 0, r0, c1, c0, 2 + orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions) + mcr p15, 0, r0, c1, c0, 2 + mov r0, #0x40000000 // Set EN bit in FPEXC + mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly + bx lr + +ASM_PFX(ArmCallWFI): + wfi + bx lr + +//Note: Return 0 in Uniprocessor implementation +ASM_PFX(ArmReadCbar): + mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register + bx lr + +ASM_PFX(ArmInvalidateInstructionAndDataTlb): + mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB + dsb + bx lr + +ASM_PFX(ArmReadMpidr): + mrc p15, 0, r0, c0, c0, 5 @ read MPIDR + bx lr ASM_FUNCTION_REMOVE_IF_UNREFERENCED |