diff options
| -rw-r--r-- | UefiCpuPkg/CpuDxe/CpuDxe.c | 5 | ||||
| -rw-r--r-- | UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 4 | ||||
| -rw-r--r-- | UefiCpuPkg/Library/MpInitLib/MpLib.c | 4 | ||||
| -rw-r--r-- | UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 8 | ||||
| -rw-r--r-- | UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 5 | ||||
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 4 |
6 files changed, 14 insertions, 16 deletions
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c index 52cc26e..efa0bc3 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c @@ -1071,7 +1071,7 @@ AddMemoryMappedIoSpace ( }
}
- DEBUG_CODE (
+ DEBUG_CODE_BEGIN ();
//
// Make sure there are adjacent descriptors covering [Base, Base + Length).
// It is possible that they have not been merged; merging can be prevented
@@ -1089,7 +1089,7 @@ AddMemoryMappedIoSpace ( ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
}
- );
+ DEBUG_CODE_END ();
FreeMemorySpaceMap:
FreePool (MemorySpaceMap);
@@ -1212,4 +1212,3 @@ InitializeCpu ( return Status;
}
-
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c index 52bd90d..7b4e730 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -243,7 +243,7 @@ GetApicMode ( VOID
)
{
- DEBUG_CODE (
+ DEBUG_CODE_BEGIN ();
{
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
@@ -259,7 +259,7 @@ GetApicMode ( ASSERT (ApicBaseMsr.Bits.EXTD == 0);
}
}
- );
+ DEBUG_CODE_END ();
return LOCAL_APIC_MODE_XAPIC;
}
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index 84c9438..b390c55 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -2155,7 +2155,7 @@ MpInitLibInitialize ( //
// Dump the microcode revision for each core.
//
- DEBUG_CODE (
+ DEBUG_CODE_BEGIN ();
UINT32 ThreadId;
UINT32 ExpectedMicrocodeRevision;
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
@@ -2176,7 +2176,7 @@ MpInitLibInitialize ( ));
}
}
- );
+ DEBUG_CODE_END ();
//
// Initialize global data for MP support
//
diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c index 2021f0c..805a2f8 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -2186,7 +2186,7 @@ MtrrSetMemoryAttributesInMtrrSettings ( //
// 0. Dump the requests.
//
- DEBUG_CODE (
+ DEBUG_CODE_BEGIN ();
DEBUG ((DEBUG_CACHE, "Mtrr: Set Mem Attribute to %a, ScratchSize = %x%a",
(MtrrSetting == NULL) ? "Hardware" : "Buffer", *ScratchSize,
(RangeCount <= 1) ? "," : "\n"
@@ -2197,7 +2197,7 @@ MtrrSetMemoryAttributesInMtrrSettings ( Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length
));
}
- );
+ DEBUG_CODE_END ();
//
// 1. Validate the parameters.
@@ -2715,7 +2715,7 @@ MtrrDebugPrintAllMtrrsWorker ( IN MTRR_SETTINGS *MtrrSetting
)
{
- DEBUG_CODE (
+ DEBUG_CODE_BEGIN ();
MTRR_SETTINGS LocalMtrrs;
MTRR_SETTINGS *Mtrrs;
UINTN Index;
@@ -2799,7 +2799,7 @@ MtrrDebugPrintAllMtrrsWorker ( Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length - 1
));
}
- );
+ DEBUG_CODE_END ();
}
/**
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index a653443..2f77ab3 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -636,7 +636,7 @@ AnalysisProcessorFeatures ( //
// Dump the last CPU feature list
//
- DEBUG_CODE (
+ DEBUG_CODE_BEGIN ();
DEBUG ((DEBUG_INFO, "Last CPU features list...\n"));
Entry = GetFirstNode (&CpuFeaturesData->FeatureList);
while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) {
@@ -659,7 +659,7 @@ AnalysisProcessorFeatures ( DumpCpuFeatureMask (PcdGetPtr (PcdCpuFeaturesSetting), CpuFeaturesData->BitMaskSize);
DEBUG ((DEBUG_INFO, "Final PcdCpuFeaturesSetting:\n"));
DumpCpuFeatureMask (CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize);
- );
+ DEBUG_CODE_END ();
//
// Save PCDs and display CPU PCDs
@@ -1190,4 +1190,3 @@ CpuFeaturesDetect ( AnalysisProcessorFeatures (CpuFeaturesData->NumberOfCpus);
}
-
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c index c8eacbb..fbf45d6 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -597,12 +597,12 @@ PiCpuSmmEntry ( // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
// A constant BSP index makes no sense because it may be hot removed.
//
- DEBUG_CODE (
+ DEBUG_CODE_BEGIN ();
if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));
}
- );
+ DEBUG_CODE_END ();
//
// Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
|