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| author | Star Zeng <star.zeng@intel.com> | 2017-07-28 22:13:00 +0800 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2017-08-01 17:49:14 +0800 |
| commit | 9e9ca2100f22be29f1a53129d741f4305ff34a71 (patch) | |
| tree | beaadcc348fe8f3f6c5f3763227d1ffa323a0dfe /UefiCpuPkg | |
| parent | 884200f95f7fbf7ffad8b304fdfb331570c74677 (diff) | |
| download | edk2-9e9ca2100f22be29f1a53129d741f4305ff34a71.zip edk2-9e9ca2100f22be29f1a53129d741f4305ff34a71.tar.gz edk2-9e9ca2100f22be29f1a53129d741f4305ff34a71.tar.bz2 | |
UefiCpuPkg SecCore: Adjust PeiTemporaryRamBase&Size to be 8byte aligned
As HOB which has 8byte aligned requirement will be built based on them
in PEI phase.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'UefiCpuPkg')
| -rw-r--r-- | UefiCpuPkg/SecCore/SecMain.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c index 077d0db..18b7782 100644 --- a/UefiCpuPkg/SecCore/SecMain.c +++ b/UefiCpuPkg/SecCore/SecMain.c @@ -1,7 +1,7 @@ /** @file
C functions in SEC
- Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -230,6 +230,12 @@ SecStartupPhase2( ASSERT (SecCoreData->PeiTemporaryRamSize > Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));
SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));
SecCoreData->PeiTemporaryRamSize = SecCoreData->PeiTemporaryRamSize - Index * sizeof (EFI_PEI_PPI_DESCRIPTOR);
+ //
+ // Adjust the Base and Size to be 8-byte aligned as HOB which has 8byte aligned requirement
+ // will be built based on them in PEI phase.
+ //
+ SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);
+ SecCoreData->PeiTemporaryRamSize &= ~0x07;
} else {
//
// No addition PPI, PpiList directly point to the common PPI list.
|