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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-01-17 13:52:06 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-01-18 09:45:38 +0800 |
| commit | 9c6961d5987c1cabe4d7136fe506f00ce1c501c8 (patch) | |
| tree | f029d9ae4437ada5f964b06553cbd2b08c859f70 /UefiCpuPkg | |
| parent | b2725f57c7a1e6feeb176f1563a4f1a8c2eb6c6f (diff) | |
| download | edk2-9c6961d5987c1cabe4d7136fe506f00ce1c501c8.zip edk2-9c6961d5987c1cabe4d7136fe506f00ce1c501c8.tar.gz edk2-9c6961d5987c1cabe4d7136fe506f00ce1c501c8.tar.bz2 | |
UefiCpuPkg/MpInitLib: Fix timer interrupt is disabled after SwitchBSP
Commits a2ea6894e6ca95e8d7a254593661a79e4b988626
* UefiCpuPkg/MpInitLib: Fix a bug that AP enters timer INT handler
masked the interrupts in AP.
But it didn't unmask the interrupt in new BSP when Switch BSP
happens.
The patch fixed this issue.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
Cc: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'UefiCpuPkg')
| -rw-r--r-- | UefiCpuPkg/Library/MpInitLib/MpLib.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index cdc0311..8ec016e 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -1771,6 +1771,7 @@ SwitchBSPWorker ( ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.BSP = 1;
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
+ ProgramVirtualWireMode ();
//
// Wait for old BSP finished AP task
|