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authorRuiyu Ni <ruiyu.ni@intel.com>2018-01-09 16:46:40 +0800
committerRuiyu Ni <ruiyu.ni@intel.com>2018-01-11 10:37:54 +0800
commit579510336e2ccbb22fa706c49baa07969e3d60f6 (patch)
treef2afb6e6543015df838b36e34f378a9adbd73403 /UefiCpuPkg
parent479a3b6053bb4c508d7397c65f482e0a8f3c9719 (diff)
downloadedk2-579510336e2ccbb22fa706c49baa07969e3d60f6.zip
edk2-579510336e2ccbb22fa706c49baa07969e3d60f6.tar.gz
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UefiCpuPkg/MtrrLib: Fix a MTRR calculation bug
80 A8 B0 B8 C0 +----------WB--------+-UC-+-WT-+-WB-+ For above memory settings, current code caused the final MTRR settings miss [A8, B0, UC] when default memory type is UC. The root cause is the code only checks the mandatory weight between A8 to B0, but skips to check the optional weight. The patch fixes this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'UefiCpuPkg')
-rw-r--r--UefiCpuPkg/Library/MtrrLib/MtrrLib.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
index fafa15f..768d4d5 100644
--- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
+++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
@@ -47,7 +47,7 @@ typedef struct {
UINT64 Address;
UINT64 Alignment;
UINT64 Length;
- UINT8 Type : 7;
+ MTRR_MEMORY_CACHE_TYPE Type : 7;
//
// Temprary use for calculating the best MTRR settings.
@@ -1429,7 +1429,7 @@ MtrrLibCalculateSubtractivePath (
while (SubStart != SubStop) {
Status = MtrrLibAppendVariableMtrr (
Mtrrs, MtrrCapacity, MtrrCount,
- Vertices[SubStart].Address, Vertices[SubStart].Length, (MTRR_MEMORY_CACHE_TYPE) Vertices[SubStart].Type
+ Vertices[SubStart].Address, Vertices[SubStart].Length, Vertices[SubStart].Type
);
if (RETURN_ERROR (Status)) {
return Status;
@@ -1450,10 +1450,11 @@ MtrrLibCalculateSubtractivePath (
Pre = Vertices[Cur].Previous;
SubStop = Pre;
- if (Weight[M (Pre, Cur)] != 0) {
+ if (Weight[M (Pre, Cur)] + Weight[O (Pre, Cur)] != 0) {
Status = MtrrLibAppendVariableMtrr (
Mtrrs, MtrrCapacity, MtrrCount,
- Vertices[Pre].Address, Vertices[Cur].Address - Vertices[Pre].Address, LowestPrecedentType
+ Vertices[Pre].Address, Vertices[Cur].Address - Vertices[Pre].Address,
+ (Pre != Cur - 1) ? LowestPrecedentType : Vertices[Pre].Type
);
if (RETURN_ERROR (Status)) {
return Status;