UefiCpuPkg: Update PiSmmCpuDxeSmm pass XCODE5 tool chain

https://bugzilla.tianocore.org/show_bug.cgi?id=849

In V2, use "mov rax, strict qword 0" to replace the hard code db.

1. Use lea instruction to get the address instead of mov instruction.
2. Use the dummy address as jmp destination, and add the logic to fix up
the address to the absolute address at boot time.
3. On MpFuncs.nasm, use ExchangeInfo to record InitializeFloatingPointUnits.
This way is same to MpInitLib.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

4 files changed, 40 insertions, 20 deletions

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm
index 702233d..704942e 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;

-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>

 ; This program and the accompanying materials

 ; are licensed and made available under the terms and conditions of the BSD License

 ; which accompanies this distribution.  The full text of the license may be found at

@@ -18,8 +18,6 @@
 ;

 ;-------------------------------------------------------------------------------

 

-extern ASM_PFX(InitializeFloatingPointUnits)

-

 %define VacantFlag 0x0

 %define NotVacantFlag 0xff

 

@@ -31,6 +29,7 @@ extern ASM_PFX(InitializeFloatingPointUnits)
 %define IdtrLocation LockLocation + 0x2A

 %define BufferStartLocation LockLocation + 0x34

 %define Cr3OffsetLocation LockLocation + 0x38

+%define InitializeFloatingPointUnitsAddress LockLocation + 0x3C

 

 ;-------------------------------------------------------------------------------------

 ;RendezvousFunnelProc  procedure follows. All APs execute their procedure. This

@@ -153,7 +152,7 @@ Releaselock:
         ;

         ; Call assembly function to initialize FPU.

         ;

-        mov         rax, ASM_PFX(InitializeFloatingPointUnits)

+        mov         rax, qword [esi + InitializeFloatingPointUnitsAddress]

         sub         rsp, 0x20

         call        rax

         add         rsp, 0x20

@@ -185,7 +184,7 @@ RendezvousFunnelProcEnd:
 ; comments here for definition of address map

 global ASM_PFX(AsmGetAddressMap)

 ASM_PFX(AsmGetAddressMap):

-        mov         rax, RendezvousFunnelProcStart

+        lea         rax, [RendezvousFunnelProcStart]

         mov         qword [rcx], rax

         mov         qword [rcx+0x8], PMODE_ENTRY - RendezvousFunnelProcStart

         mov         qword [rcx+0x10], FLAT32_JUMP - RendezvousFunnelProcStart

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index dc56dc7..697fd2b 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;

-; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>

 ; This program and the accompanying materials

 ; are licensed and made available under the terms and conditions of the BSD License

 ; which accompanies this distribution.  The full text of the license may be found at

@@ -158,7 +158,8 @@ Base:
     mov     cr0, rbx

     retf

 @LongMode:                              ; long mode (64-bit code) starts here

-    mov     rax, ASM_PFX(gSmiHandlerIdtr)

+    mov     rax, strict qword 0         ;  mov     rax, ASM_PFX(gSmiHandlerIdtr)

+SmiHandlerIdtrAbsAddr:

     lidt    [rax]

     lea     ebx, [rdi + DSC_OFFSET]

     mov     ax, [rbx + DSC_DS]

@@ -169,7 +170,9 @@ Base:
     mov     gs, eax

     mov     ax, [rbx + DSC_SS]

     mov     ss, eax

-;   jmp     _SmiHandler                 ; instruction is not needed

+    mov     rax, strict qword 0         ;   mov     rax, _SmiHandler

+_SmiHandlerAbsAddr:

+    jmp     rax

 

 _SmiHandler:

     mov     rbx, [rsp + 0x8]             ; rcx <- CpuIndex

@@ -184,16 +187,13 @@ _SmiHandler:
     add     rsp, -0x20

 

     mov     rcx, rbx

-    mov     rax, ASM_PFX(CpuSmmDebugEntry)

-    call    rax

+    call    ASM_PFX(CpuSmmDebugEntry)

 

     mov     rcx, rbx

-    mov     rax, ASM_PFX(SmiRendezvous)  ; rax <- absolute addr of SmiRedezvous

-    call    rax

+    call    ASM_PFX(SmiRendezvous)

 

     mov     rcx, rbx

-    mov     rax, ASM_PFX(CpuSmmDebugExit)

-    call    rax

+    call    ASM_PFX(CpuSmmDebugExit)

 

     add     rsp, 0x20

 

@@ -205,7 +205,7 @@ _SmiHandler:
 

     add     rsp, 0x200

 

-    mov     rax, ASM_PFX(mXdSupported)

+    lea     rax, [ASM_PFX(mXdSupported)]

     mov     al, [rax]

     cmp     al, 0

     jz      .1

@@ -222,3 +222,13 @@ _SmiHandler:
 

 ASM_PFX(gcSmiHandlerSize)    DW      $ - _SmiEntryPoint

 

+global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)

+ASM_PFX(PiSmmCpuSmiEntryFixupAddress):

+    lea    rax, [ASM_PFX(gSmiHandlerIdtr)]

+    lea    rcx, [SmiHandlerIdtrAbsAddr]

+    mov    qword [rcx - 8], rax

+

+    lea    rax, [_SmiHandler]

+    lea    rcx, [_SmiHandlerAbsAddr]

+    mov    qword [rcx - 8], rax

+    ret

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
index b2e2e6d..a8a9af3 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;

-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>

 ; This program and the accompanying materials

 ; are licensed and made available under the terms and conditions of the BSD License

 ; which accompanies this distribution.  The full text of the license may be found at

@@ -289,7 +289,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile):
 

 ;; call into exception handler

     mov     rcx, [rbp + 8]

-    mov     rax, ASM_PFX(SmiPFHandler)

+    lea     rax, [ASM_PFX(SmiPFHandler)]

 

 ;; Prepare parameter and call

     mov     rdx, rsp

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 9d05e2c..2701689 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;

-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>

 ; This program and the accompanying materials

 ; are licensed and made available under the terms and conditions of the BSD License

 ; which accompanies this distribution.  The full text of the license may be found at

@@ -60,7 +60,7 @@ ASM_PFX(gSmmCr4): DD 0
 ASM_PFX(gSmmCr0): DD 0

     mov     cr0, rax                    ; enable protected mode & paging

     DB      0x66, 0xea                   ; far jmp to long mode

-ASM_PFX(gSmmJmpAddr): DQ @LongMode

+ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode

 @LongMode:                              ; long-mode starts here

     DB      0x48, 0xbc                   ; mov rsp, imm64

 ASM_PFX(gSmmInitStack): DQ 0

@@ -99,7 +99,7 @@ ASM_PFX(gcSmmInitTemplate):
     sub ebp, 0x30000

     jmp ebp

 @L1:

-    DQ      ASM_PFX(SmmStartup)

+    DQ     0; ASM_PFX(SmmStartup)

 

 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)

 

@@ -128,3 +128,14 @@ ASM_PFX(mRebasedFlagAddr32): dd 0
     ;

     db      0xff, 0x25

 ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0

+

+global ASM_PFX(PiSmmCpuSmmInitFixupAddress)

+ASM_PFX(PiSmmCpuSmmInitFixupAddress):

+    lea    rax, [@LongMode]

+    lea    rcx, [ASM_PFX(gSmmJmpAddr)]

+    mov    qword [rcx], rax

+

+    lea    rax, [ASM_PFX(SmmStartup)]

+    lea    rcx, [@L1]

+    mov    qword [rcx], rax

+    ret