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| author | Sami Mujawar <sami.mujawar@arm.com> | 2023-09-22 15:35:10 +0100 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-10-30 12:16:56 +0000 |
| commit | 2b0d117b4b4ea44b213fc3b10c9e59fa96510c83 (patch) | |
| tree | f80364c8712ccdbfe4718f7e12f7e4ba6372a688 /ShellPkg | |
| parent | 50e8518276d9c7de3cb9593a482901d3a936a2b7 (diff) | |
| download | edk2-2b0d117b4b4ea44b213fc3b10c9e59fa96510c83.zip edk2-2b0d117b4b4ea44b213fc3b10c9e59fa96510c83.tar.gz edk2-2b0d117b4b4ea44b213fc3b10c9e59fa96510c83.tar.bz2 | |
ShellPkg: Acpiview: Update MADT parser for TRBE interrupt
ACPI 6.5 introduces a new filed to the MADT GICC
structure to specify the TRBE interrupt. The TRBE
interrupt is a Processor Private interrupt (PPI)
and is used to specify a platform-specific
interrupt to signal TRBE events.
Therefore, update the MADT GICC structure parser
to parse the new TRBE interrupt field. Also, add
validations to check that the TRBE interrupt is
within the PPI interrupt range.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Diffstat (limited to 'ShellPkg')
| -rw-r--r-- | ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Madt/MadtParser.c | 48 |
1 files changed, 46 insertions, 2 deletions
diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Madt/MadtParser.c b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Madt/MadtParser.c index 41edcb9..3a4f246 100644 --- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Madt/MadtParser.c +++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Madt/MadtParser.c @@ -1,7 +1,7 @@ /** @file
MADT table parser
- Copyright (c) 2016 - 2020, ARM Limited. All rights reserved.
+ Copyright (c) 2016 - 2023, ARM Limited. All rights reserved.
Copyright (c) 2022, AMD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -98,6 +98,48 @@ ValidateSpeOverflowInterrupt ( }
/**
+ This function validates the TRBE Interrupt in the GICC.
+
+ @param [in] Ptr Pointer to the start of the field data.
+ @param [in] Context Pointer to context specific information e.g. this
+ could be a pointer to the ACPI table header.
+**/
+STATIC
+VOID
+EFIAPI
+ValidateTrbeInterrupt (
+ IN UINT8 *Ptr,
+ IN VOID *Context
+ )
+{
+ UINT16 TrbeInterrupt;
+
+ TrbeInterrupt = *(UINT16 *)Ptr;
+
+ // SPE not supported by this processor
+ if (TrbeInterrupt == 0) {
+ return;
+ }
+
+ if ((TrbeInterrupt < ARM_PPI_ID_MIN) ||
+ ((TrbeInterrupt > ARM_PPI_ID_MAX) &&
+ (TrbeInterrupt < ARM_PPI_ID_EXTENDED_MIN)) ||
+ (TrbeInterrupt > ARM_PPI_ID_EXTENDED_MAX))
+ {
+ IncrementErrorCount ();
+ Print (
+ L"\nERROR: TRBE Interrupt ID of %d is not in the allowed PPI ID "
+ L"ranges of %d-%d or %d-%d (for GICv3.1 or later).",
+ TrbeInterrupt,
+ ARM_PPI_ID_MIN,
+ ARM_PPI_ID_MAX,
+ ARM_PPI_ID_EXTENDED_MIN,
+ ARM_PPI_ID_EXTENDED_MAX
+ );
+ }
+}
+
+/**
An ACPI_PARSER array describing the GICC Interrupt Controller Structure.
**/
STATIC CONST ACPI_PARSER GicCParser[] = {
@@ -122,7 +164,9 @@ STATIC CONST ACPI_PARSER GicCParser[] = { NULL },
{ L"Reserved", 1, 77, L"0x%x", NULL, NULL, NULL, NULL },
{ L"SPE overflow Interrupt", 2, 78, L"0x%x", NULL, NULL,
- ValidateSpeOverflowInterrupt, NULL }
+ ValidateSpeOverflowInterrupt, NULL },
+ { L"TRBE Interrupt", 2, 80, L"0x%x", NULL, NULL,
+ ValidateTrbeInterrupt, NULL }
};
/**
|