OvmfPkg: Create GHCB pages for use during Pei and Dxe phase

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198

Allocate memory for the GHCB pages and the per-CPU variable pages during
SEV initialization for use during Pei and Dxe phases. The GHCB page(s)
must be shared pages, so clear the encryption mask from the current page
table entries. Upon successful allocation, set the GHCB PCDs (PcdGhcbBase
and PcdGhcbSize).

The per-CPU variable page needs to be unique per AP. Using the page after
the GHCB ensures that it is unique per AP. Only the GHCB page is marked as
shared, keeping the per-CPU variable page encyrpted. The same logic is
used in DXE using CreateIdentityMappingPageTables() before switching to
the DXE pagetables.

The GHCB pages (one per vCPU) will be used by the PEI and DXE #VC
exception handlers. The #VC exception handler will fill in the necessary
fields of the GHCB and exit to the hypervisor using the VMGEXIT
instruction. The hypervisor then accesses the GHCB associated with the
vCPU in order to perform the requested function.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>

5 files changed, 52 insertions, 1 deletions

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index f84f23f..133a9a9 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -608,6 +608,8 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0

 

   # Set SEV-ES defaults

+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0

+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0

   gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0

 

 !if $(SMM_REQUIRE) == TRUE

diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index a66abcc..338c38d 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -620,6 +620,8 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0

 

   # Set SEV-ES defaults

+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0

+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0

   gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0

 

 !if $(SMM_REQUIRE) == TRUE

diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 2a8975f..b80710f 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -618,6 +618,8 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0

 

   # Set SEV-ES defaults

+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0

+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0

   gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0

 

 !if $(SMM_REQUIRE) == TRUE

diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c
index 4dc5340..4fd4534 100644
--- a/OvmfPkg/PlatformPei/AmdSev.c
+++ b/OvmfPkg/PlatformPei/AmdSev.c
@@ -10,12 +10,15 @@
 // The package level header files this module uses

 //

 #include <IndustryStandard/Q35MchIch9.h>

+#include <Library/BaseMemoryLib.h>

 #include <Library/DebugLib.h>

 #include <Library/HobLib.h>

 #include <Library/MemEncryptSevLib.h>

+#include <Library/MemoryAllocationLib.h>

 #include <Library/PcdLib.h>

 #include <PiPei.h>

 #include <Register/Amd/Cpuid.h>

+#include <Register/Amd/Msr.h>

 #include <Register/Cpuid.h>

 #include <Register/Intel/SmramSaveStateMap.h>

 

@@ -32,7 +35,10 @@ AmdSevEsInitialize (
   VOID

   )

 {

-  RETURN_STATUS     PcdStatus;

+  VOID              *GhcbBase;

+  PHYSICAL_ADDRESS  GhcbBasePa;

+  UINTN             GhcbPageCount, PageCount;

+  RETURN_STATUS     PcdStatus, DecryptStatus;

 

   if (!MemEncryptSevEsIsEnabled ()) {

     return;

@@ -40,6 +46,43 @@ AmdSevEsInitialize (
 

   PcdStatus = PcdSetBoolS (PcdSevEsIsEnabled, TRUE);

   ASSERT_RETURN_ERROR (PcdStatus);

+

+  //

+  // Allocate GHCB and per-CPU variable pages.

+  //

+  GhcbPageCount = mMaxCpuCount * 2;

+  GhcbBase = AllocatePages (GhcbPageCount);

+  ASSERT (GhcbBase != NULL);

+

+  GhcbBasePa = (PHYSICAL_ADDRESS)(UINTN) GhcbBase;

+

+  //

+  // Each vCPU gets two consecutive pages, the first is the GHCB and the

+  // second is the per-CPU variable page. Loop through the allocation and

+  // only clear the encryption mask for the GHCB pages.

+  //

+  for (PageCount = 0; PageCount < GhcbPageCount; PageCount += 2) {

+    DecryptStatus = MemEncryptSevClearPageEncMask (

+      0,

+      GhcbBasePa + EFI_PAGES_TO_SIZE (PageCount),

+      1,

+      TRUE

+      );

+    ASSERT_RETURN_ERROR (DecryptStatus);

+  }

+

+  ZeroMem (GhcbBase, EFI_PAGES_TO_SIZE (GhcbPageCount));

+

+  PcdStatus = PcdSet64S (PcdGhcbBase, GhcbBasePa);

+  ASSERT_RETURN_ERROR (PcdStatus);

+  PcdStatus = PcdSet64S (PcdGhcbSize, EFI_PAGES_TO_SIZE (GhcbPageCount));

+  ASSERT_RETURN_ERROR (PcdStatus);

+

+  DEBUG ((DEBUG_INFO,

+    "SEV-ES is enabled, %lu GHCB pages allocated starting at 0x%p\n",

+    (UINT64)GhcbPageCount, GhcbBase));

+

+  AsmWriteMsr64 (MSR_SEV_ES_GHCB, GhcbBasePa);

 }

 

 /**

diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf
index a54d10b..4742e1b 100644
--- a/OvmfPkg/PlatformPei/PlatformPei.inf
+++ b/OvmfPkg/PlatformPei/PlatformPei.inf
@@ -102,6 +102,8 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack

   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable

   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask

+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase

+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize

   gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy

   gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress

   gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber