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authorLaszlo Ersek <lersek@redhat.com>2019-09-20 17:07:43 +0200
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2020-02-05 12:59:32 +0000
commitadec2bd598dac8a6378d6244089158ed8d656f62 (patch)
treebd0d632ebb2518ae65201de9f8dff4bb682d30d6 /OvmfPkg/PlatformPei
parent73974f809cbfc2b4cecec539b2eb8635b0e42eff (diff)
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OvmfPkg/PlatformPei: assert there's no permanent PEI RAM at default SMBASE
The permanent PEI RAM that is published on the normal boot path starts strictly above MEMFD_BASE_ADDRESS (8 MB -- see the FDF files), regardless of whether PEI decompression will be necessary on S3 resume due to SMM_REQUIRE. Therefore the normal boot permanent PEI RAM never overlaps with the SMRAM at the default SMBASE (192 KB). The S3 resume permanent PEI RAM is strictly above the normal boot one. Therefore the no-overlap statement holds true on the S3 resume path as well. Assert the no-overlap condition commonly for both boot paths in PublishPeiMemory(). Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200129214412.2361-7-lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'OvmfPkg/PlatformPei')
-rw-r--r--OvmfPkg/PlatformPei/MemDetect.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 2bc1c46..4879ee8 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -17,6 +17,7 @@ Module Name:
#include <IndustryStandard/I440FxPiix4.h>
#include <IndustryStandard/Q35MchIch9.h>
#include <PiPei.h>
+#include <Register/Intel/SmramSaveStateMap.h>
//
// The Library classes this module consumes
@@ -627,6 +628,15 @@ PublishPeiMemory (
}
//
+ // MEMFD_BASE_ADDRESS separates the SMRAM at the default SMBASE from the
+ // normal boot permanent PEI RAM. Regarding the S3 boot path, the S3
+ // permanent PEI RAM is located even higher.
+ //
+ if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {
+ ASSERT (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE <= MemoryBase);
+ }
+
+ //
// Publish this memory to the PEI Core
//
Status = PublishSystemMemory(MemoryBase, MemorySize);