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| author | Laszlo Ersek <lersek@redhat.com> | 2019-05-29 11:51:44 +0200 |
|---|---|---|
| committer | Laszlo Ersek <lersek@redhat.com> | 2019-06-03 19:54:01 +0200 |
| commit | 753d3d6f43b2c2bf2df67038608496663ff6e3aa (patch) | |
| tree | df1e761ae1ad1c09f01d44a3c223b37ce397ba80 /OvmfPkg/PlatformPei | |
| parent | eb4d62b0779c3a5766174e4373c95a8b6a967cb7 (diff) | |
| download | edk2-753d3d6f43b2c2bf2df67038608496663ff6e3aa.zip edk2-753d3d6f43b2c2bf2df67038608496663ff6e3aa.tar.gz edk2-753d3d6f43b2c2bf2df67038608496663ff6e3aa.tar.bz2 | |
Revert "OvmfPkg/PlatformPei: hoist PciBase assignment above the i440fx/q35 branching"
This reverts commit 9a2e8d7c65ef7f39c6754d27e52954b616bc6628.
The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.
QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.
Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'OvmfPkg/PlatformPei')
| -rw-r--r-- | OvmfPkg/PlatformPei/Platform.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 9c01361..5e0a154 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -181,7 +181,6 @@ MemMapInitialization ( TopOfLowRam = GetSystemMemorySizeBelow4gb ();
PciExBarBase = 0;
- PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
//
// The MMCONFIG area is expected to fall between the top of low RAM and
@@ -193,6 +192,7 @@ MemMapInitialization ( PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
PciSize = 0xFC000000 - PciBase;
} else {
+ PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
PciSize = 0xFC000000 - PciBase;
}
|