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| author | Laszlo Ersek <lersek@redhat.com> | 2016-02-26 16:29:19 +0100 |
|---|---|---|
| committer | Laszlo Ersek <lersek@redhat.com> | 2016-03-03 18:18:28 +0100 |
| commit | 03845e90cc432cc59da44aa9fc3bd7b18288c201 (patch) | |
| tree | dff334bd502592a64f75e5de9f603519758371d7 /OvmfPkg/PlatformPei/Platform.c | |
| parent | e705f899aff3c918a597f7bd95e72823bbebc51f (diff) | |
| download | edk2-03845e90cc432cc59da44aa9fc3bd7b18288c201.zip edk2-03845e90cc432cc59da44aa9fc3bd7b18288c201.tar.gz edk2-03845e90cc432cc59da44aa9fc3bd7b18288c201.tar.bz2 | |
OvmfPkg: factor the MMIO aperture shared by all PCI root bridges into PCDs
Going forward, two modules will need to know about the aperture:
PlatformPei (as before), and OVMF's upcoming PciHostBridgeLib instance
(because the core PciHostBridgeDxe driver requires the library to state
the exact apertures for all root bridges).
On QEMU, all root bridges share the same MMIO aperture, hence one pair of
PCDs suffices.
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'OvmfPkg/PlatformPei/Platform.c')
| -rw-r--r-- | OvmfPkg/PlatformPei/Platform.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 1df0f38..7d09412 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -213,6 +213,7 @@ MemMapInitialization ( if (!mXen) {
UINT32 TopOfLowRam;
UINT32 PciBase;
+ UINT32 PciSize;
TopOfLowRam = GetSystemMemorySizeBelow4gb ();
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
@@ -240,7 +241,10 @@ MemMapInitialization ( // 0xFED20000 gap 896 KB
// 0xFEE00000 LAPIC 1 MB
//
- AddIoMemoryRangeHob (PciBase, 0xFC000000);
+ PciSize = 0xFC000000 - PciBase;
+ AddIoMemoryBaseSizeHob (PciBase, PciSize);
+ PcdSet64 (PcdPciMmio32Base, PciBase);
+ PcdSet64 (PcdPciMmio32Size, PciSize);
AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
|