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| author | Laszlo Ersek <lersek@redhat.com> | 2015-05-13 09:31:49 +0000 |
|---|---|---|
| committer | lersek <lersek@Edk2> | 2015-05-13 09:31:49 +0000 |
| commit | da372167684822ddd0cce01e5282502da28538a4 (patch) | |
| tree | 4093007f5a3a9f9df64bb3956eade8fde692b9fe /OvmfPkg/Library/AcpiTimerLib | |
| parent | bc9d05d6f2ba3267cbf2f339cecd59d2ebae4ffb (diff) | |
| download | edk2-da372167684822ddd0cce01e5282502da28538a4.zip edk2-da372167684822ddd0cce01e5282502da28538a4.tar.gz edk2-da372167684822ddd0cce01e5282502da28538a4.tar.bz2 | |
OvmfPkg: consolidate POWER_MGMT_REGISTER_PIIX4() on "I440FxPiix4.h" macros
All POWER_MGMT_REGISTER_PIIX4() macro invocations in OvmfPkg should use
the macros in "I440FxPiix4.h" as arguments.
Cc: Gabriel Somlo <somlo@cmu.edu>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17435 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'OvmfPkg/Library/AcpiTimerLib')
| -rw-r--r-- | OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c | 7 | ||||
| -rw-r--r-- | OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c | 9 | ||||
| -rw-r--r-- | OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c | 2 |
3 files changed, 8 insertions, 10 deletions
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c index c20f299..490cf80 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c @@ -22,7 +22,6 @@ // Power Management PCI Configuration Register fields
//
#define PMBA_RTE BIT0
-#define PIIX4_PMIOSE BIT0
//
// Offset in the Power Management Base Address to the ACPI Timer
@@ -58,9 +57,9 @@ AcpiTimerLibConstructor ( HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC
- AcpiEnBit = PIIX4_PMIOSE;
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c index 55f3572..50a3391 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c @@ -23,7 +23,6 @@ // Power Management PCI Configuration Register fields
//
#define PMBA_RTE BIT0
-#define PIIX4_PMIOSE BIT0
//
// Offset in the Power Management Base Address to the ACPI Timer
@@ -56,9 +55,9 @@ AcpiTimerLibConstructor ( HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC
- AcpiEnBit = PIIX4_PMIOSE;
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
@@ -114,7 +113,7 @@ InternalAcpiGetTimerTick ( HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
diff --git a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c index 649b5c9..0c42ed2 100644 --- a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c @@ -61,7 +61,7 @@ AcpiTimerLibConstructor ( HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);
switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
|