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| author | Heyi Guo <heyi.guo@linaro.org> | 2018-03-15 15:17:43 +0800 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-03-15 08:07:14 +0000 |
| commit | ac9b530e6b47c0957345e421b618d8bdd2bf21cf (patch) | |
| tree | 53a8feec5f18fc9773412f4dce8f639d8737f97a /OvmfPkg/IoMmuDxe | |
| parent | b3fa393f477a12fe0e1aedb36395ca9b345ae110 (diff) | |
| download | edk2-ac9b530e6b47c0957345e421b618d8bdd2bf21cf.zip edk2-ac9b530e6b47c0957345e421b618d8bdd2bf21cf.tar.gz edk2-ac9b530e6b47c0957345e421b618d8bdd2bf21cf.tar.bz2 | |
ArmPkg/TimerDxe: Add ISB for timer compare value reload
If timer interrupt is level sensitive, reloading timer compare
register has a side effect of clearing GIC pending status, so a "ISB"
is needed to make sure this instruction is executed before enabling
CPU IRQ, or else we may get spurious timer interrupts.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'OvmfPkg/IoMmuDxe')
0 files changed, 0 insertions, 0 deletions