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| author | Leo Duran <leo.duran@amd.com> | 2018-05-25 03:07:30 +0800 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2018-06-11 10:40:20 +0800 |
| commit | a05a8a5aa17da4bc7144706a9931d68beec1a61f (patch) | |
| tree | d2f86f2f51f3b86627264e7aa2580a7645f21abd /Nt32Pkg | |
| parent | eb5943134630292db2c14346b5d94eab0b72314f (diff) | |
| download | edk2-a05a8a5aa17da4bc7144706a9931d68beec1a61f.zip edk2-a05a8a5aa17da4bc7144706a9931d68beec1a61f.tar.gz edk2-a05a8a5aa17da4bc7144706a9931d68beec1a61f.tar.bz2 | |
MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode
Put the UART in FIFO Polled Mode by clearing IER after setting FCR.
Also, add comments to show DLAB state for registers 0 and 1.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leo Duran <leo.duran@amd.com>
Cc: Star Zeng <star.zeng@intel.com>
CC: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'Nt32Pkg')
0 files changed, 0 insertions, 0 deletions