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| author | Michael Kinney <michael.d.kinney@intel.com> | 2015-04-30 07:25:07 +0000 |
|---|---|---|
| committer | erictian <erictian@Edk2> | 2015-04-30 07:25:07 +0000 |
| commit | 6f7878a97281299bf4a052687a177dfbee4b0de1 (patch) | |
| tree | db19b5da9e625f14db1ed88dd480d553c1df8fde /MdePkg | |
| parent | 2bbe9553c495bb9024b4b51743142a0a50e0d370 (diff) | |
| download | edk2-6f7878a97281299bf4a052687a177dfbee4b0de1.zip edk2-6f7878a97281299bf4a052687a177dfbee4b0de1.tar.gz edk2-6f7878a97281299bf4a052687a177dfbee4b0de1.tar.bz2 | |
MdePkg/BaseLib: Preserve EBX register and fix stack offset to LinearAddress in AsmFlushCacheLine()
The value of EBX must be preserved to follow IA32 cdecl calling convention in the assembly
implementation of AsmFlushCacheLine(). The CPUID instruction modifies the EBX register.
The EBX register value is saved onto the stack before CPUID and restored from the stack
after CPUID.
The update to the inline assembly implementation of AsmFlushCacheLine() changed the location of the
LinearAddress parameter value on the stack. The hardcoded lookup using [esp + 4] is not correct.
Use the parameter name LinearAddress instead of the hard coded [esp + 4] stack location to prevent
this issue from occurring again if there are changes to the inline assembly in the future.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17279 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg')
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm | 2 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm index a64f96b..1979f6d 100644 --- a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm +++ b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm @@ -39,7 +39,9 @@ AsmFlushCacheLine PROC ; then promote flush range to flush entire cache.
;
mov eax, 1
+ push ebx
cpuid
+ pop ebx
mov eax, [esp + 4]
test edx, BIT19
jz @F
diff --git a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c index 7ad12ab..7ac4af3 100644 --- a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c +++ b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c @@ -45,7 +45,7 @@ AsmFlushCacheLine ( cpuid
test edx, BIT19
jz NoClflush
- mov eax, [esp + 4]
+ mov eax, dword ptr [LinearAddress]
clflush [eax]
jmp Done
NoClflush:
|