MdePkg/BaseLib: Support IA32 processors without CLFLUSH

Use CPUID Leaf 01 to detect support for CLFLUSH instruction.  

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17212 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 15 insertions, 2 deletions

diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseLib/Ia32/GccInline.c
index 02af3f6..f52a1fe 100644
--- a/MdePkg/Library/BaseLib/Ia32/GccInline.c
+++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c
@@ -1,7 +1,7 @@
 /** @file

   GCC inline implementation of BaseLib processor specific functions.

   

-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>

   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -1745,6 +1745,19 @@ AsmFlushCacheLine (
   IN      VOID                      *LinearAddress

   )

 {

+  UINT32  RegEdx;

+

+  //

+  // If the CPU does not support CLFLUSH instruction, 

+  // then promote flush range to flush entire cache.

+  //

+  AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx);

+  if ((RegEdx & BIT19) == 0) {

+    __asm__ __volatile__ ("wbinvd":::"memory");

+    return LinearAddress;

+  }

+

+

   __asm__ __volatile__ (

     "clflush (%0)"

     : "+a" (LinearAddress) 

@@ -1752,7 +1765,7 @@ AsmFlushCacheLine (
     : "memory"

     );

     

-    return LinearAddress;

+  return LinearAddress;

 }