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authorNeo Hsueh <Hong-Chih.Hsueh@amd.com>2024-05-01 14:13:39 -0500
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2024-06-05 12:22:53 +0000
commit10cd8b45ce36152996bcb1520ba36107a8cdc63f (patch)
tree7f7753739ee78813fb55b0b2b556b08429b08e1d /MdePkg/Include/Register/Intel
parente2e09d8512898709a3d076fdd36c8abee2734027 (diff)
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MdePkg: Remove non-ASCII characters from header file
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4775 Signed-off-by: Neo Hsueh <Hong-Chih.Hsueh@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Jiangang He <jiangang.he@amd.com>
Diffstat (limited to 'MdePkg/Include/Register/Intel')
-rw-r--r--MdePkg/Include/Register/Intel/ArchitecturalMsr.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
index 756e7c8..4715c59 100644
--- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
+++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
@@ -5733,9 +5733,9 @@ typedef union {
/// [Bit 7:4] TME Policy/Encryption Algorithm: Only algorithms enumerated in
/// IA32_TME_CAPABILITY are allowed.
/// For example:
- /// 0000 – AES-XTS-128.
- /// 0001 – AES-XTS-128 with integrity.
- /// 0010 – AES-XTS-256.
+ /// 0000 - AES-XTS-128.
+ /// 0001 - AES-XTS-128 with integrity.
+ /// 0010 - AES-XTS-256.
/// Other values are invalid.
///
UINT32 TmePolicy : 4;
@@ -5756,7 +5756,7 @@ typedef union {
/// Similar to enumeration, this is an encoded value.
/// Writing a value greater than MK_TME_MAX_KEYID_BITS will result in #GP.
/// Writing a non-zero value to this field will #GP if bit 1 of EAX (Hardware
- /// Encryption Enable) is not also set to ‘1, as encryption hardware must be
+ /// Encryption Enable) is not also set to 1, as encryption hardware must be
/// enabled to use MKTME.
/// Example: To support 255 keys, this field would be set to a value of 8.
///