MdePkg: Apply uncrustify changes

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the MdePkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>

3 files changed, 313 insertions, 317 deletions

diff --git a/MdePkg/Include/Register/Amd/Cpuid.h b/MdePkg/Include/Register/Amd/Cpuid.h
index 8e91e84..44394fc 100644
--- a/MdePkg/Include/Register/Amd/Cpuid.h
+++ b/MdePkg/Include/Register/Amd/Cpuid.h
@@ -42,7 +42,6 @@ CPUID Signature Information
 /// @}

 ///

 

-

 /**

   CPUID Extended Processor Signature and Features

 

@@ -70,36 +69,36 @@ typedef union {
     ///

     /// [Bits 3:0] Stepping.

     ///

-    UINT32  Stepping:4;

+    UINT32    Stepping   : 4;

     ///

     /// [Bits 7:4] Base Model.

     ///

-    UINT32  BaseModel:4;

+    UINT32    BaseModel  : 4;

     ///

     /// [Bits 11:8] Base Family.

     ///

-    UINT32  BaseFamily:4;

+    UINT32    BaseFamily : 4;

     ///

     /// [Bit 15:12] Reserved.

     ///

-    UINT32  Reserved1:4;

+    UINT32    Reserved1  : 4;

     ///

     /// [Bits 19:16] Extended Model.

     ///

-    UINT32  ExtModel:4;

+    UINT32    ExtModel   : 4;

     ///

     /// [Bits 27:20] Extended Family.

     ///

-    UINT32  ExtFamily:8;

+    UINT32    ExtFamily  : 8;

     ///

     /// [Bit 31:28] Reserved.

     ///

-    UINT32  Reserved2:4;

+    UINT32    Reserved2  : 4;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_AMD_EXTENDED_CPU_SIG_EAX;

 

 /**

@@ -114,16 +113,16 @@ typedef union {
     ///

     /// [Bits 27:0] Reserved.

     ///

-    UINT32  Reserved:28;

+    UINT32    Reserved : 28;

     ///

     /// [Bit 31:28] Package Type.

     ///

-    UINT32  PkgType:4;

+    UINT32    PkgType  : 4;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_AMD_EXTENDED_CPU_SIG_EBX;

 

 /**

@@ -138,116 +137,116 @@ typedef union {
     ///

     /// [Bit 0] LAHF/SAHF available in 64-bit mode.

     ///

-    UINT32  LAHF_SAHF:1;

+    UINT32    LAHF_SAHF               : 1;

     ///

     /// [Bit 1] Core multi-processing legacy mode.

     ///

-    UINT32  CmpLegacy:1;

+    UINT32    CmpLegacy               : 1;

     ///

     /// [Bit 2] Secure Virtual Mode feature.

     ///

-    UINT32  SVM:1;

+    UINT32    SVM                     : 1;

     ///

     /// [Bit 3] Extended APIC register space.

     ///

-    UINT32  ExtApicSpace:1;

+    UINT32    ExtApicSpace            : 1;

     ///

     /// [Bit 4] LOCK MOV CR0 means MOV CR8.

     ///

-    UINT32  AltMovCr8:1;

+    UINT32    AltMovCr8               : 1;

     ///

     /// [Bit 5] LZCNT instruction support.

     ///

-    UINT32  LZCNT:1;

+    UINT32    LZCNT                   : 1;

     ///

     /// [Bit 6] SSE4A instruction support.

     ///

-    UINT32  SSE4A:1;

+    UINT32    SSE4A                   : 1;

     ///

     /// [Bit 7] Misaligned SSE Mode.

     ///

-    UINT32  MisAlignSse:1;

+    UINT32    MisAlignSse             : 1;

     ///

     /// [Bit 8] ThreeDNow Prefetch instructions.

     ///

-    UINT32  PREFETCHW:1;

+    UINT32    PREFETCHW               : 1;

     ///

     /// [Bit 9] OS Visible Work-around support.

     ///

-    UINT32  OSVW:1;

+    UINT32    OSVW                    : 1;

     ///

     /// [Bit 10] Instruction Based Sampling.

     ///

-    UINT32  IBS:1;

+    UINT32    IBS                     : 1;

     ///

     /// [Bit 11] Extended Operation Support.

     ///

-    UINT32  XOP:1;

+    UINT32    XOP                     : 1;

     ///

     /// [Bit 12] SKINIT and STGI support.

     ///

-    UINT32  SKINIT:1;

+    UINT32    SKINIT                  : 1;

     ///

     /// [Bit 13] Watchdog Timer support.

     ///

-    UINT32  WDT:1;

+    UINT32    WDT                     : 1;

     ///

     /// [Bit 14] Reserved.

     ///

-    UINT32  Reserved1:1;

+    UINT32    Reserved1               : 1;

     ///

     /// [Bit 15] Lightweight Profiling support.

     ///

-    UINT32  LWP:1;

+    UINT32    LWP                     : 1;

     ///

     /// [Bit 16] 4-Operand FMA instruction support.

     ///

-    UINT32  FMA4:1;

+    UINT32    FMA4                    : 1;

     ///

     /// [Bit 17] Translation Cache Extension.

     ///

-    UINT32  TCE:1;

+    UINT32    TCE                     : 1;

     ///

     /// [Bit 21:18] Reserved.

     ///

-    UINT32  Reserved2:4;

+    UINT32    Reserved2               : 4;

     ///

     /// [Bit 22] Topology Extensions support.

     ///

-    UINT32  TopologyExtensions:1;

+    UINT32    TopologyExtensions      : 1;

     ///

     /// [Bit 23] Core Performance Counter Extensions.

     ///

-    UINT32  PerfCtrExtCore:1;

+    UINT32    PerfCtrExtCore          : 1;

     ///

     /// [Bit 25:24] Reserved.

     ///

-    UINT32  Reserved3:2;

+    UINT32    Reserved3               : 2;

     ///

     /// [Bit 26] Data Breakpoint Extension.

     ///

-    UINT32  DataBreakpointExtension:1;

+    UINT32    DataBreakpointExtension : 1;

     ///

     /// [Bit 27] Performance Time-Stamp Counter.

     ///

-    UINT32  PerfTsc:1;

+    UINT32    PerfTsc                 : 1;

     ///

     /// [Bit 28] L3 Performance Counter Extensions.

     ///

-    UINT32  PerfCtrExtL3:1;

+    UINT32    PerfCtrExtL3            : 1;

     ///

     /// [Bit 29] MWAITX and MONITORX capability.

     ///

-    UINT32  MwaitExtended:1;

+    UINT32    MwaitExtended           : 1;

     ///

     /// [Bit 31:30] Reserved.

     ///

-    UINT32  Reserved4:2;

+    UINT32    Reserved4               : 2;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_AMD_EXTENDED_CPU_SIG_ECX;

 

 /**

@@ -262,135 +261,134 @@ typedef union {
     ///

     /// [Bit 0] x87 floating point unit on-chip.

     ///

-    UINT32  FPU:1;

+    UINT32    FPU            : 1;

     ///

     /// [Bit 1] Virtual-mode enhancements.

     ///

-    UINT32  VME:1;

+    UINT32    VME            : 1;

     ///

     /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.

     ///

-    UINT32  DE:1;

+    UINT32    DE             : 1;

     ///

     /// [Bit 3] Page-size extensions (4 MB pages).

     ///

-    UINT32  PSE:1;

+    UINT32    PSE            : 1;

     ///

     /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.

     ///

-    UINT32  TSC:1;

+    UINT32    TSC            : 1;

     ///

     /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.

     ///

-    UINT32  MSR:1;

+    UINT32    MSR            : 1;

     ///

     /// [Bit 6] Physical-address extensions (PAE).

     ///

-    UINT32  PAE:1;

+    UINT32    PAE            : 1;

     ///

     /// [Bit 7] Machine check exception, CR4.MCE.

     ///

-    UINT32  MCE:1;

+    UINT32    MCE            : 1;

     ///

     /// [Bit 8] CMPXCHG8B instruction.

     ///

-    UINT32  CMPXCHG8B:1;

+    UINT32    CMPXCHG8B      : 1;

     ///

     /// [Bit 9] APIC exists and is enabled.

     ///

-    UINT32  APIC:1;

+    UINT32    APIC           : 1;

     ///

     /// [Bit 10] Reserved.

     ///

-    UINT32  Reserved1:1;

+    UINT32    Reserved1      : 1;

     ///

     /// [Bit 11] SYSCALL and SYSRET instructions.

     ///

-    UINT32  SYSCALL_SYSRET:1;

+    UINT32    SYSCALL_SYSRET : 1;

     ///

     /// [Bit 12] Memory-type range registers.

     ///

-    UINT32  MTRR:1;

+    UINT32    MTRR           : 1;

     ///

     /// [Bit 13] Page global extension, CR4.PGE.

     ///

-    UINT32  PGE:1;

+    UINT32    PGE            : 1;

     ///

     /// [Bit 14] Machine check architecture, MCG_CAP.

     ///

-    UINT32  MCA:1;

+    UINT32    MCA            : 1;

     ///

     /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.

     ///

-    UINT32  CMOV:1;

+    UINT32    CMOV           : 1;

     ///

     /// [Bit 16] Page attribute table.

     ///

-    UINT32  PAT:1;

+    UINT32    PAT            : 1;

     ///

     /// [Bit 17] Page-size extensions.

     ///

-    UINT32  PSE36 : 1;

+    UINT32    PSE36          : 1;

     ///

     /// [Bit 19:18] Reserved.

     ///

-    UINT32  Reserved2:2;

+    UINT32    Reserved2      : 2;

     ///

     /// [Bit 20] No-execute page protection.

     ///

-    UINT32  NX:1;

+    UINT32    NX             : 1;

     ///

     /// [Bit 21] Reserved.

     ///

-    UINT32  Reserved3:1;

+    UINT32    Reserved3      : 1;

     ///

     /// [Bit 22] AMD Extensions to MMX instructions.

     ///

-    UINT32  MmxExt:1;

+    UINT32    MmxExt         : 1;

     ///

     /// [Bit 23] MMX instructions.

     ///

-    UINT32  MMX:1;

+    UINT32    MMX            : 1;

     ///

     /// [Bit 24] FXSAVE and FXRSTOR instructions.

     ///

-    UINT32  FFSR:1;

+    UINT32    FFSR           : 1;

     ///

     /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.

     ///

-    UINT32  FFXSR:1;

+    UINT32    FFXSR          : 1;

     ///

     /// [Bit 26] 1-GByte large page support.

     ///

-    UINT32  Page1GB:1;

+    UINT32    Page1GB        : 1;

     ///

     /// [Bit 27] RDTSCP instructions.

     ///

-    UINT32  RDTSCP:1;

+    UINT32    RDTSCP         : 1;

     ///

     /// [Bit 28] Reserved.

     ///

-    UINT32  Reserved4:1;

+    UINT32    Reserved4      : 1;

     ///

     /// [Bit 29] Long Mode.

     ///

-    UINT32  LM:1;

+    UINT32    LM             : 1;

     ///

     /// [Bit 30] 3DNow! instructions.

     ///

-    UINT32  ThreeDNow:1;

+    UINT32    ThreeDNow      : 1;

     ///

     /// [Bit 31] AMD Extensions to 3DNow! instructions.

     ///

-    UINT32  ThreeDNowExt:1;

+    UINT32    ThreeDNowExt   : 1;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_AMD_EXTENDED_CPU_SIG_EDX;

 

-

 /**

 CPUID Linear Physical Address Size

 

@@ -417,24 +415,24 @@ typedef union {
     ///

     /// [Bits 7:0] Maximum physical byte address size in bits.

     ///

-    UINT32  PhysicalAddressBits:8;

+    UINT32    PhysicalAddressBits : 8;

     ///

     /// [Bits 15:8] Maximum linear byte address size in bits.

     ///

-    UINT32  LinearAddressBits:8;

+    UINT32    LinearAddressBits   : 8;

     ///

     /// [Bits 23:16] Maximum guest physical byte address size in bits.

     ///

-    UINT32  GuestPhysAddrSize:8;

+    UINT32    GuestPhysAddrSize   : 8;

     ///

     /// [Bit 31:24] Reserved.

     ///

-    UINT32  Reserved:8;

+    UINT32    Reserved            : 8;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;

 

 /**

@@ -449,24 +447,24 @@ typedef union {
     ///

     /// [Bits 0] Clear Zero Instruction.

     ///

-    UINT32  CLZERO:1;

+    UINT32    CLZERO     : 1;

     ///

     /// [Bits 1] Instructions retired count support.

     ///

-    UINT32  IRPerf:1;

+    UINT32    IRPerf     : 1;

     ///

     /// [Bits 2] Restore error pointers for XSave instructions.

     ///

-    UINT32  XSaveErPtr:1;

+    UINT32    XSaveErPtr : 1;

     ///

     /// [Bit 31:3] Reserved.

     ///

-    UINT32  Reserved:29;

+    UINT32    Reserved   : 29;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;

 

 /**

@@ -481,31 +479,30 @@ typedef union {
     ///

     /// [Bits 7:0] Number of threads - 1.

     ///

-    UINT32  NC:8;

+    UINT32    NC               : 8;

     ///

     /// [Bit 11:8] Reserved.

     ///

-    UINT32  Reserved1:4;

+    UINT32    Reserved1        : 4;

     ///

     /// [Bits 15:12] APIC ID size.

     ///

-    UINT32  ApicIdCoreIdSize:4;

+    UINT32    ApicIdCoreIdSize : 4;

     ///

     /// [Bits 17:16] Performance time-stamp counter size.

     ///

-    UINT32  PerfTscSize:2;

+    UINT32    PerfTscSize      : 2;

     ///

     /// [Bit 31:18] Reserved.

     ///

-    UINT32  Reserved2:14;

+    UINT32    Reserved2        : 14;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;

 

-

 /**

   CPUID AMD Processor Topology

 

@@ -519,7 +516,7 @@ typedef union {
                 CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.

   @retval  EDX  Reserved.

 **/

-#define CPUID_AMD_PROCESSOR_TOPOLOGY             0x8000001E

+#define CPUID_AMD_PROCESSOR_TOPOLOGY  0x8000001E

 

 /**

   CPUID AMD Processor Topology EAX for CPUID leaf

@@ -533,12 +530,12 @@ typedef union {
     ///

     /// [Bit 31:0] Extended APIC Id.

     ///

-    UINT32  ExtendedApicId;

+    UINT32    ExtendedApicId;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;

 

 /**

@@ -553,20 +550,20 @@ typedef union {
     ///

     /// [Bits 7:0] Core Id.

     ///

-    UINT32  CoreId:8;

+    UINT32    CoreId         : 8;

     ///

     /// [Bits 15:8] Threads per core.

     ///

-    UINT32  ThreadsPerCore:8;

+    UINT32    ThreadsPerCore : 8;

     ///

     /// [Bit 31:16] Reserved.

     ///

-    UINT32  Reserved:16;

+    UINT32    Reserved       : 16;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;

 

 /**

@@ -581,23 +578,22 @@ typedef union {
     ///

     /// [Bits 7:0] Node Id.

     ///

-    UINT32  NodeId:8;

+    UINT32    NodeId            : 8;

     ///

     /// [Bits 10:8] Nodes per processor.

     ///

-    UINT32  NodesPerProcessor:3;

+    UINT32    NodesPerProcessor : 3;

     ///

     /// [Bit 31:11] Reserved.

     ///

-    UINT32  Reserved:21;

+    UINT32    Reserved          : 21;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;

 

-

 /**

   CPUID Memory Encryption Information

 

@@ -621,7 +617,7 @@ typedef union {
   @endcode

 **/

 

-#define CPUID_MEMORY_ENCRYPTION_INFO             0x8000001F

+#define CPUID_MEMORY_ENCRYPTION_INFO  0x8000001F

 

 /**

   CPUID Memory Encryption support information EAX for CPUID leaf

@@ -635,32 +631,32 @@ typedef union {
     ///

     /// [Bit 0] Secure Memory Encryption (Sme) Support

     ///

-    UINT32  SmeBit:1;

+    UINT32    SmeBit          : 1;

 

     ///

     /// [Bit 1] Secure Encrypted Virtualization (Sev) Support

     ///

-    UINT32  SevBit:1;

+    UINT32    SevBit          : 1;

 

     ///

     /// [Bit 2] Page flush MSR support

     ///

-    UINT32  PageFlushMsrBit:1;

+    UINT32    PageFlushMsrBit : 1;

 

     ///

     /// [Bit 3] Encrypted state support

     ///

-    UINT32  SevEsBit:1;

+    UINT32    SevEsBit        : 1;

 

     ///

     /// [Bit 31:4] Reserved

     ///

-    UINT32  ReservedBits:28;

+    UINT32    ReservedBits    : 28;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_MEMORY_ENCRYPTION_INFO_EAX;

 

 /**

@@ -675,23 +671,23 @@ typedef union {
     ///

     /// [Bit 5:0] Page table bit number used to enable memory encryption

     ///

-    UINT32  PtePosBits:6;

+    UINT32    PtePosBits      : 6;

 

     ///

     /// [Bit 11:6] Reduction of system physical address space bits when

     ///  memory encryption is enabled

     ///

-    UINT32  ReducedPhysBits:5;

+    UINT32    ReducedPhysBits : 5;

 

     ///

     /// [Bit 31:12] Reserved

     ///

-    UINT32  ReservedBits:21;

+    UINT32    ReservedBits    : 21;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_MEMORY_ENCRYPTION_INFO_EBX;

 

 /**

@@ -706,12 +702,12 @@ typedef union {
     ///

     /// [Bit 31:0] Number of encrypted guest supported simultaneously

     ///

-    UINT32  NumGuests;

+    UINT32    NumGuests;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_MEMORY_ENCRYPTION_INFO_ECX;

 

 /**

@@ -726,12 +722,12 @@ typedef union {
     ///

     /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID

     ///

-    UINT32  MinAsid;

+    UINT32    MinAsid;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

 } CPUID_MEMORY_ENCRYPTION_INFO_EDX;

 

 #endif

diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Register/Amd/Fam17Msr.h
index 6201485..bb4e143 100644
--- a/MdePkg/Include/Register/Amd/Fam17Msr.h
+++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
@@ -21,82 +21,82 @@
   Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register

 

 **/

-#define MSR_SEV_ES_GHCB                    0xc0010130

+#define MSR_SEV_ES_GHCB  0xc0010130

 

 /**

   MSR information returned for #MSR_SEV_ES_GHCB

 **/

 typedef union {

   struct {

-    UINT32  Function:12;

-    UINT32  Reserved1:20;

-    UINT32  Reserved2:32;

+    UINT32    Function  : 12;

+    UINT32    Reserved1 : 20;

+    UINT32    Reserved2 : 32;

   } GhcbInfo;

 

   struct {

-    UINT8   Reserved[3];

-    UINT8   SevEncryptionBitPos;

-    UINT16  SevEsProtocolMin;

-    UINT16  SevEsProtocolMax;

+    UINT8     Reserved[3];

+    UINT8     SevEncryptionBitPos;

+    UINT16    SevEsProtocolMin;

+    UINT16    SevEsProtocolMax;

   } GhcbProtocol;

 

   struct {

-    UINT32  Function:12;

-    UINT32  ReasonCodeSet:4;

-    UINT32  ReasonCode:8;

-    UINT32  Reserved1:8;

-    UINT32  Reserved2:32;

+    UINT32    Function      : 12;

+    UINT32    ReasonCodeSet : 4;

+    UINT32    ReasonCode    : 8;

+    UINT32    Reserved1     : 8;

+    UINT32    Reserved2     : 32;

   } GhcbTerminate;

 

   struct {

-    UINT64  Function:12;

-    UINT64  Features:52;

+    UINT64    Function : 12;

+    UINT64    Features : 52;

   } GhcbHypervisorFeatures;

 

   struct {

-    UINT64  Function:12;

-    UINT64  GuestFrameNumber:52;

+    UINT64    Function         : 12;

+    UINT64    GuestFrameNumber : 52;

   } GhcbGpaRegister;

 

   struct {

-    UINT64 Function:12;

-    UINT64 GuestFrameNumber:40;

-    UINT64 Operation:4;

-    UINT64 Reserved:8;

+    UINT64    Function         : 12;

+    UINT64    GuestFrameNumber : 40;

+    UINT64    Operation        : 4;

+    UINT64    Reserved         : 8;

   } SnpPageStateChangeRequest;

 

   struct {

-    UINT32 Function:12;

-    UINT32 Reserved:20;

-    UINT32 ErrorCode;

+    UINT32    Function : 12;

+    UINT32    Reserved : 20;

+    UINT32    ErrorCode;

   } SnpPageStateChangeResponse;

 

-  VOID    *Ghcb;

+  VOID      *Ghcb;

 

-  UINT64  GhcbPhysicalAddress;

+  UINT64    GhcbPhysicalAddress;

 } MSR_SEV_ES_GHCB_REGISTER;

 

-#define GHCB_INFO_SEV_INFO                          1

-#define GHCB_INFO_SEV_INFO_GET                      2

-#define GHCB_INFO_CPUID_REQUEST                     4

-#define GHCB_INFO_CPUID_RESPONSE                    5

-#define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST         18

-#define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE        19

-#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_REQUEST     20

-#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_RESPONSE    21

-#define GHCB_HYPERVISOR_FEATURES_REQUEST            128

-#define GHCB_HYPERVISOR_FEATURES_RESPONSE           129

-#define GHCB_INFO_TERMINATE_REQUEST                 256

-

-#define GHCB_TERMINATE_GHCB                0

-#define GHCB_TERMINATE_GHCB_GENERAL        0

-#define GHCB_TERMINATE_GHCB_PROTOCOL       1

+#define GHCB_INFO_SEV_INFO                        1

+#define GHCB_INFO_SEV_INFO_GET                    2

+#define GHCB_INFO_CPUID_REQUEST                   4

+#define GHCB_INFO_CPUID_RESPONSE                  5

+#define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST       18

+#define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE      19

+#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_REQUEST   20

+#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_RESPONSE  21

+#define GHCB_HYPERVISOR_FEATURES_REQUEST          128

+#define GHCB_HYPERVISOR_FEATURES_RESPONSE         129

+#define GHCB_INFO_TERMINATE_REQUEST               256

+

+#define GHCB_TERMINATE_GHCB           0

+#define GHCB_TERMINATE_GHCB_GENERAL   0

+#define GHCB_TERMINATE_GHCB_PROTOCOL  1

 

 /**

   Secure Encrypted Virtualization (SEV) status register

 

 **/

-#define MSR_SEV_STATUS                     0xc0010131

+#define MSR_SEV_STATUS  0xc0010131

 

 /**

   MSR information returned for #MSR_SEV_STATUS

@@ -109,28 +109,28 @@ typedef union {
     ///

     /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled

     ///

-    UINT32  SevBit:1;

+    UINT32    SevBit    : 1;

 

     ///

     /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled

     ///

-    UINT32  SevEsBit:1;

+    UINT32    SevEsBit  : 1;

 

     ///

     /// [Bit 2] Secure Nested Paging (SevSnp) is enabled

     ///

-    UINT32  SevSnpBit:1;

+    UINT32    SevSnpBit : 1;

 

-    UINT32  Reserved2:29;

+    UINT32    Reserved2 : 29;

   } Bits;

   ///

   /// All bit fields as a 32-bit value

   ///

-  UINT32  Uint32;

+  UINT32    Uint32;

   ///

   /// All bit fields as a 64-bit value

   ///

-  UINT64  Uint64;

+  UINT64    Uint64;

 } MSR_SEV_STATUS_REGISTER;

 

 #endif

diff --git a/MdePkg/Include/Register/Amd/Ghcb.h b/MdePkg/Include/Register/Amd/Ghcb.h
index 8c5f46e..e7626a2 100644
--- a/MdePkg/Include/Register/Amd/Ghcb.h
+++ b/MdePkg/Include/Register/Amd/Ghcb.h
@@ -20,69 +20,69 @@
 #include <Library/DebugLib.h>

 

 #define UD_EXCEPTION  6

-#define GP_EXCEPTION 13

-#define VC_EXCEPTION 29

+#define GP_EXCEPTION  13

+#define VC_EXCEPTION  29

 

-#define GHCB_VERSION_MIN     1

-#define GHCB_VERSION_MAX     1

+#define GHCB_VERSION_MIN  1

+#define GHCB_VERSION_MAX  1

 

 #define GHCB_STANDARD_USAGE  0

 

 //

 // SVM Exit Codes

 //

-#define SVM_EXIT_DR7_READ       0x27ULL

-#define SVM_EXIT_DR7_WRITE      0x37ULL

-#define SVM_EXIT_RDTSC          0x6EULL

-#define SVM_EXIT_RDPMC          0x6FULL

-#define SVM_EXIT_CPUID          0x72ULL

-#define SVM_EXIT_INVD           0x76ULL

-#define SVM_EXIT_IOIO_PROT      0x7BULL

-#define SVM_EXIT_MSR            0x7CULL

-#define SVM_EXIT_VMMCALL        0x81ULL

-#define SVM_EXIT_RDTSCP         0x87ULL

-#define SVM_EXIT_WBINVD         0x89ULL

-#define SVM_EXIT_MONITOR        0x8AULL

-#define SVM_EXIT_MWAIT          0x8BULL

-#define SVM_EXIT_NPF            0x400ULL

+#define SVM_EXIT_DR7_READ   0x27ULL

+#define SVM_EXIT_DR7_WRITE  0x37ULL

+#define SVM_EXIT_RDTSC      0x6EULL

+#define SVM_EXIT_RDPMC      0x6FULL

+#define SVM_EXIT_CPUID      0x72ULL

+#define SVM_EXIT_INVD       0x76ULL

+#define SVM_EXIT_IOIO_PROT  0x7BULL

+#define SVM_EXIT_MSR        0x7CULL

+#define SVM_EXIT_VMMCALL    0x81ULL

+#define SVM_EXIT_RDTSCP     0x87ULL

+#define SVM_EXIT_WBINVD     0x89ULL

+#define SVM_EXIT_MONITOR    0x8AULL

+#define SVM_EXIT_MWAIT      0x8BULL

+#define SVM_EXIT_NPF        0x400ULL

 

 //

 // VMG Special Exit Codes

 //

-#define SVM_EXIT_MMIO_READ                      0x80000001ULL

-#define SVM_EXIT_MMIO_WRITE                     0x80000002ULL

-#define SVM_EXIT_NMI_COMPLETE                   0x80000003ULL

-#define SVM_EXIT_AP_RESET_HOLD                  0x80000004ULL

-#define SVM_EXIT_AP_JUMP_TABLE                  0x80000005ULL

-#define SVM_EXIT_SNP_PAGE_STATE_CHANGE          0x80000010ULL

-#define SVM_EXIT_SNP_AP_CREATION                0x80000013ULL

-#define SVM_EXIT_HYPERVISOR_FEATURES            0x8000FFFDULL

-#define SVM_EXIT_UNSUPPORTED                    0x8000FFFFULL

+#define SVM_EXIT_MMIO_READ              0x80000001ULL

+#define SVM_EXIT_MMIO_WRITE             0x80000002ULL

+#define SVM_EXIT_NMI_COMPLETE           0x80000003ULL

+#define SVM_EXIT_AP_RESET_HOLD          0x80000004ULL

+#define SVM_EXIT_AP_JUMP_TABLE          0x80000005ULL

+#define SVM_EXIT_SNP_PAGE_STATE_CHANGE  0x80000010ULL

+#define SVM_EXIT_SNP_AP_CREATION        0x80000013ULL

+#define SVM_EXIT_HYPERVISOR_FEATURES    0x8000FFFDULL

+#define SVM_EXIT_UNSUPPORTED            0x8000FFFFULL

 

 //

 // IOIO Exit Information

 //

-#define IOIO_TYPE_STR       BIT2

-#define IOIO_TYPE_IN        1

-#define IOIO_TYPE_INS       (IOIO_TYPE_IN | IOIO_TYPE_STR)

-#define IOIO_TYPE_OUT       0

-#define IOIO_TYPE_OUTS      (IOIO_TYPE_OUT | IOIO_TYPE_STR)

-

-#define IOIO_REP            BIT3

-

-#define IOIO_ADDR_64        BIT9

-#define IOIO_ADDR_32        BIT8

-#define IOIO_ADDR_16        BIT7

-

-#define IOIO_DATA_32        BIT6

-#define IOIO_DATA_16        BIT5

-#define IOIO_DATA_8         BIT4

-#define IOIO_DATA_MASK      (BIT6 | BIT5 | BIT4)

-#define IOIO_DATA_OFFSET    4

+#define IOIO_TYPE_STR   BIT2

+#define IOIO_TYPE_IN    1

+#define IOIO_TYPE_INS   (IOIO_TYPE_IN | IOIO_TYPE_STR)

+#define IOIO_TYPE_OUT   0

+#define IOIO_TYPE_OUTS  (IOIO_TYPE_OUT | IOIO_TYPE_STR)

+

+#define IOIO_REP  BIT3

+

+#define IOIO_ADDR_64  BIT9

+#define IOIO_ADDR_32  BIT8

+#define IOIO_ADDR_16  BIT7

+

+#define IOIO_DATA_32      BIT6

+#define IOIO_DATA_16      BIT5

+#define IOIO_DATA_8       BIT4

+#define IOIO_DATA_MASK    (BIT6 | BIT5 | BIT4)

+#define IOIO_DATA_OFFSET  4

 #define IOIO_DATA_BYTES(x)  (((x) & IOIO_DATA_MASK) >> IOIO_DATA_OFFSET)

 

-#define IOIO_SEG_ES         0

-#define IOIO_SEG_DS         (BIT11 | BIT10)

+#define IOIO_SEG_ES  0

+#define IOIO_SEG_DS  (BIT11 | BIT10)

 

 //

 // AP Creation Information

@@ -92,54 +92,54 @@
 #define SVM_VMGEXIT_SNP_AP_DESTROY         2

 

 typedef PACKED struct {

-  UINT8                  Reserved1[203];

-  UINT8                  Cpl;

-  UINT8                  Reserved8[300];

-  UINT64                 Rax;

-  UINT8                  Reserved4[264];

-  UINT64                 Rcx;

-  UINT64                 Rdx;

-  UINT64                 Rbx;

-  UINT8                  Reserved5[112];

-  UINT64                 SwExitCode;

-  UINT64                 SwExitInfo1;

-  UINT64                 SwExitInfo2;

-  UINT64                 SwScratch;

-  UINT8                  Reserved6[56];

-  UINT64                 XCr0;

-  UINT8                  ValidBitmap[16];

-  UINT64                 X87StateGpa;

-  UINT8                  Reserved7[1016];

+  UINT8     Reserved1[203];

+  UINT8     Cpl;

+  UINT8     Reserved8[300];

+  UINT64    Rax;

+  UINT8     Reserved4[264];

+  UINT64    Rcx;

+  UINT64    Rdx;

+  UINT64    Rbx;

+  UINT8     Reserved5[112];

+  UINT64    SwExitCode;

+  UINT64    SwExitInfo1;

+  UINT64    SwExitInfo2;

+  UINT64    SwScratch;

+  UINT8     Reserved6[56];

+  UINT64    XCr0;

+  UINT8     ValidBitmap[16];

+  UINT64    X87StateGpa;

+  UINT8     Reserved7[1016];

 } GHCB_SAVE_AREA;

 

 typedef PACKED struct {

-  GHCB_SAVE_AREA         SaveArea;

-  UINT8                  SharedBuffer[2032];

-  UINT8                  Reserved1[10];

-  UINT16                 ProtocolVersion;

-  UINT32                 GhcbUsage;

+  GHCB_SAVE_AREA    SaveArea;

+  UINT8             SharedBuffer[2032];

+  UINT8             Reserved1[10];

+  UINT16            ProtocolVersion;

+  UINT32            GhcbUsage;

 } GHCB;

 

 #define GHCB_SAVE_AREA_QWORD_OFFSET(RegisterField) \

   (OFFSET_OF (GHCB, SaveArea.RegisterField) / sizeof (UINT64))

 

 typedef enum {

-  GhcbCpl          = GHCB_SAVE_AREA_QWORD_OFFSET (Cpl),

-  GhcbRax          = GHCB_SAVE_AREA_QWORD_OFFSET (Rax),

-  GhcbRbx          = GHCB_SAVE_AREA_QWORD_OFFSET (Rbx),

-  GhcbRcx          = GHCB_SAVE_AREA_QWORD_OFFSET (Rcx),

-  GhcbRdx          = GHCB_SAVE_AREA_QWORD_OFFSET (Rdx),

-  GhcbXCr0         = GHCB_SAVE_AREA_QWORD_OFFSET (XCr0),

-  GhcbSwExitCode   = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitCode),

-  GhcbSwExitInfo1  = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo1),

-  GhcbSwExitInfo2  = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo2),

-  GhcbSwScratch    = GHCB_SAVE_AREA_QWORD_OFFSET (SwScratch),

+  GhcbCpl         = GHCB_SAVE_AREA_QWORD_OFFSET (Cpl),

+  GhcbRax         = GHCB_SAVE_AREA_QWORD_OFFSET (Rax),

+  GhcbRbx         = GHCB_SAVE_AREA_QWORD_OFFSET (Rbx),

+  GhcbRcx         = GHCB_SAVE_AREA_QWORD_OFFSET (Rcx),

+  GhcbRdx         = GHCB_SAVE_AREA_QWORD_OFFSET (Rdx),

+  GhcbXCr0        = GHCB_SAVE_AREA_QWORD_OFFSET (XCr0),

+  GhcbSwExitCode  = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitCode),

+  GhcbSwExitInfo1 = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo1),

+  GhcbSwExitInfo2 = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo2),

+  GhcbSwScratch   = GHCB_SAVE_AREA_QWORD_OFFSET (SwScratch),

 } GHCB_REGISTER;

 

 typedef union {

   struct {

-    UINT32  Lower32Bits;

-    UINT32  Upper32Bits;

+    UINT32    Lower32Bits;

+    UINT32    Upper32Bits;

   } Elements;

 

   UINT64    Uint64;

@@ -147,12 +147,12 @@ typedef union {
 

 typedef union {

   struct {

-    UINT32  Vector:8;

-    UINT32  Type:3;

-    UINT32  ErrorCodeValid:1;

-    UINT32  Rsvd:19;

-    UINT32  Valid:1;

-    UINT32  ErrorCode;

+    UINT32    Vector         : 8;

+    UINT32    Type           : 3;

+    UINT32    ErrorCodeValid : 1;

+    UINT32    Rsvd           : 19;

+    UINT32    Valid          : 1;

+    UINT32    ErrorCode;

   } Elements;

 

   UINT64    Uint64;

@@ -166,40 +166,40 @@ typedef union {
 //

 // Hypervisor features

 //

-#define GHCB_HV_FEATURES_SNP                              BIT0

-#define GHCB_HV_FEATURES_SNP_AP_CREATE                    (GHCB_HV_FEATURES_SNP | BIT1)

-#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION         (GHCB_HV_FEATURES_SNP_AP_CREATE | BIT2)

-#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER   (GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION | BIT3)

+#define GHCB_HV_FEATURES_SNP                             BIT0

+#define GHCB_HV_FEATURES_SNP_AP_CREATE                   (GHCB_HV_FEATURES_SNP | BIT1)

+#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION        (GHCB_HV_FEATURES_SNP_AP_CREATE | BIT2)

+#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER  (GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION | BIT3)

 

 //

 // SNP Page State Change.

 //

 // Note that the PSMASH and UNSMASH operations are not supported when using the MSR protocol.

 //

-#define SNP_PAGE_STATE_PRIVATE              1

-#define SNP_PAGE_STATE_SHARED               2

-#define SNP_PAGE_STATE_PSMASH               3

-#define SNP_PAGE_STATE_UNSMASH              4

+#define SNP_PAGE_STATE_PRIVATE  1

+#define SNP_PAGE_STATE_SHARED   2

+#define SNP_PAGE_STATE_PSMASH   3

+#define SNP_PAGE_STATE_UNSMASH  4

 

 typedef struct {

-  UINT64  CurrentPage:12;

-  UINT64  GuestFrameNumber:40;

-  UINT64  Operation:4;

-  UINT64  PageSize:1;

-  UINT64  Reserved:7;

+  UINT64    CurrentPage      : 12;

+  UINT64    GuestFrameNumber : 40;

+  UINT64    Operation        : 4;

+  UINT64    PageSize         : 1;

+  UINT64    Reserved         : 7;

 } SNP_PAGE_STATE_ENTRY;

 

 typedef struct {

-  UINT16 CurrentEntry;

-  UINT16 EndEntry;

-  UINT32 Reserved;

+  UINT16    CurrentEntry;

+  UINT16    EndEntry;

+  UINT32    Reserved;

 } SNP_PAGE_STATE_HEADER;

 

-#define SNP_PAGE_STATE_MAX_ENTRY            253

+#define SNP_PAGE_STATE_MAX_ENTRY  253

 

 typedef struct {

-  SNP_PAGE_STATE_HEADER  Header;

-  SNP_PAGE_STATE_ENTRY   Entry[SNP_PAGE_STATE_MAX_ENTRY];

+  SNP_PAGE_STATE_HEADER    Header;

+  SNP_PAGE_STATE_ENTRY     Entry[SNP_PAGE_STATE_MAX_ENTRY];

 } SNP_PAGE_STATE_CHANGE_INFO;

 

 //

@@ -217,22 +217,22 @@ typedef struct {
 #define SEV_ES_RESET_CODE_SEGMENT_TYPE  0xA

 #define SEV_ES_RESET_DATA_SEGMENT_TYPE  0x2

 

-#define SEV_ES_RESET_LDT_TYPE           0x2

-#define SEV_ES_RESET_TSS_TYPE           0x3

+#define SEV_ES_RESET_LDT_TYPE  0x2

+#define SEV_ES_RESET_TSS_TYPE  0x3

 

 #pragma pack (1)

 typedef union {

-    struct {

-      UINT16  Type:4;

-      UINT16  Sbit:1;

-      UINT16  Dpl:2;

-      UINT16  Present:1;

-      UINT16  Avl:1;

-      UINT16  Reserved1:1;

-      UINT16  Db:1;

-      UINT16  Granularity:1;

-    } Bits;

-    UINT16  Uint16;

+  struct {

+    UINT16    Type        : 4;

+    UINT16    Sbit        : 1;

+    UINT16    Dpl         : 2;

+    UINT16    Present     : 1;

+    UINT16    Avl         : 1;

+    UINT16    Reserved1   : 1;

+    UINT16    Db          : 1;

+    UINT16    Granularity : 1;

+  } Bits;

+  UINT16    Uint16;

 } SEV_ES_SEGMENT_REGISTER_ATTRIBUTES;

 

 typedef struct {

@@ -243,39 +243,39 @@ typedef struct {
 } SEV_ES_SEGMENT_REGISTER;

 

 typedef struct {

-  SEV_ES_SEGMENT_REGISTER  Es;

-  SEV_ES_SEGMENT_REGISTER  Cs;

-  SEV_ES_SEGMENT_REGISTER  Ss;

-  SEV_ES_SEGMENT_REGISTER  Ds;

-  SEV_ES_SEGMENT_REGISTER  Fs;

-  SEV_ES_SEGMENT_REGISTER  Gs;

-  SEV_ES_SEGMENT_REGISTER  Gdtr;

-  SEV_ES_SEGMENT_REGISTER  Ldtr;

-  SEV_ES_SEGMENT_REGISTER  Idtr;

-  SEV_ES_SEGMENT_REGISTER  Tr;

-  UINT8                    Reserved1[42];

-  UINT8                    Vmpl;

-  UINT8                    Reserved2[5];

-  UINT64                   Efer;

-  UINT8                    Reserved3[112];

-  UINT64                   Cr4;

-  UINT8                    Reserved4[8];

-  UINT64                   Cr0;

-  UINT64                   Dr7;

-  UINT64                   Dr6;

-  UINT64                   Rflags;

-  UINT64                   Rip;

-  UINT8                    Reserved5[232];

-  UINT64                   GPat;

-  UINT8                    Reserved6[320];

-  UINT64                   SevFeatures;

-  UINT8                    Reserved7[48];

-  UINT64                   XCr0;

-  UINT8                    Reserved8[24];

-  UINT32                   Mxcsr;

-  UINT16                   X87Ftw;

-  UINT8                    Reserved9[2];

-  UINT16                   X87Fcw;

+  SEV_ES_SEGMENT_REGISTER    Es;

+  SEV_ES_SEGMENT_REGISTER    Cs;

+  SEV_ES_SEGMENT_REGISTER    Ss;

+  SEV_ES_SEGMENT_REGISTER    Ds;

+  SEV_ES_SEGMENT_REGISTER    Fs;

+  SEV_ES_SEGMENT_REGISTER    Gs;

+  SEV_ES_SEGMENT_REGISTER    Gdtr;

+  SEV_ES_SEGMENT_REGISTER    Ldtr;

+  SEV_ES_SEGMENT_REGISTER    Idtr;

+  SEV_ES_SEGMENT_REGISTER    Tr;

+  UINT8                      Reserved1[42];

+  UINT8                      Vmpl;

+  UINT8                      Reserved2[5];

+  UINT64                     Efer;

+  UINT8                      Reserved3[112];

+  UINT64                     Cr4;

+  UINT8                      Reserved4[8];

+  UINT64                     Cr0;

+  UINT64                     Dr7;

+  UINT64                     Dr6;

+  UINT64                     Rflags;

+  UINT64                     Rip;

+  UINT8                      Reserved5[232];

+  UINT64                     GPat;

+  UINT8                      Reserved6[320];

+  UINT64                     SevFeatures;

+  UINT8                      Reserved7[48];

+  UINT64                     XCr0;

+  UINT8                      Reserved8[24];

+  UINT32                     Mxcsr;

+  UINT16                     X87Ftw;

+  UINT8                      Reserved9[2];

+  UINT16                     X87Fcw;

 } SEV_ES_SAVE_AREA;

 #pragma pack ()