Add PeiCore module for enabling NT32Pkg, please attention this PeiCore does follows PI specification except some FV definitions.

Also the old definition of MdeModulePkg/Include/Ppi/LoadFile.h and EFI_PEI_STARTUP_DESCRIPTOR in MdePkg/Include/PiPei.h will be removed when enabling PI.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@3029 6f19259b-4bc3-4df7-8a09-765794883524

5 files changed, 491 insertions, 0 deletions

diff --git a/MdeModulePkg/Core/Pei/Ipf/IpfCpuCore.i b/MdeModulePkg/Core/Pei/Ipf/IpfCpuCore.i
new file mode 100644
index 0000000..548271a
--- /dev/null
+++ b/MdeModulePkg/Core/Pei/Ipf/IpfCpuCore.i
@@ -0,0 +1,98 @@
+//++

+// Copyright (c) 2006, Intel Corporation                                                         

+// All rights reserved. This program and the accompanying materials                          

+// are licensed and made available under the terms and conditions of the BSD License         

+// which accompanies this distribution.  The full text of the license may be found at        

+// http://opensource.org/licenses/bsd-license.php                                            

+//                                                                                           

+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+// 

+// Module Name:

+//  

+//   IpfCpuCore.i

+//

+// Abstract:

+//   IPF CPU definitions

+//

+//--

+

+#ifndef _IPF_CPU_CORE_

+#define _IPF_CPU_CORE_

+

+//

+// Include common header file for this module.

+//

+#include "CommonHeader.h"

+

+#define  PEI_BSP_STORE_SIZE                     0x4000

+#define  ResetFn                                0x00

+#define  MachineCheckFn                         0x01

+#define  InitFn                                 0x02

+#define  RecoveryFn                             0x03

+#define  GuardBand                              0x10 

+

+//

+// Define hardware RSE Configuration Register

+//

+

+//

+// RS Configuration (RSC) bit field positions

+//

+#define RSC_MODE       0

+#define RSC_PL         2

+#define RSC_BE         4

+//

+// RSC bits 5-15 reserved

+//

+#define RSC_MBZ0       5

+#define RSC_MBZ0_V     0x3ff

+#define RSC_LOADRS     16

+#define RSC_LOADRS_LEN 14

+//

+// RSC bits 30-63 reserved

+//

+#define RSC_MBZ1       30

+#define RSC_MBZ1_V     0x3ffffffffULL

+

+//

+// RSC modes

+//

+

+//

+// Lazy

+//

+#define RSC_MODE_LY (0x0)

+//

+// Store intensive

+//

+#define RSC_MODE_SI (0x1)

+//

+// Load intensive

+//

+#define RSC_MODE_LI (0x2)

+//

+// Eager

+//

+#define RSC_MODE_EA (0x3)

+

+//

+// RSC Endian bit values

+//

+#define RSC_BE_LITTLE 0

+#define RSC_BE_BIG    1

+

+//

+// RSC while in kernel: enabled, little endian, pl = 0, eager mode

+//

+#define RSC_KERNEL ((RSC_MODE_EA<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))

+//

+// Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode

+//

+#define RSC_KERNEL_LAZ ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))

+//

+// RSE disabled: disabled, pl = 0, little endian, eager mode

+//

+#define RSC_KERNEL_DISABLED ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))

+

+#endif

diff --git a/MdeModulePkg/Core/Pei/Ipf/IpfCpuCore.s b/MdeModulePkg/Core/Pei/Ipf/IpfCpuCore.s
new file mode 100644
index 0000000..b66192e
--- /dev/null
+++ b/MdeModulePkg/Core/Pei/Ipf/IpfCpuCore.s
@@ -0,0 +1,197 @@
+//

+// Include common header file for this module.

+//

+#include "CommonHeader.h"

+

+//++

+// Copyright (c) 2006, Intel Corporation

+// All rights reserved. This program and the accompanying materials

+// are licensed and made available under the terms and conditions of the BSD License

+// which accompanies this distribution.  The full text of the license may be found at

+// http://opensource.org/licenses/bsd-license.php

+//                                                                                           

+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+//

+//  Module Name:

+//

+//    IpfCpuCore.s

+//

+//  Abstract:

+//    IPF Specific assembly routines

+//

+//--

+

+.file  "IpfCpuCore.s"

+

+#include  "IpfMacro.i"

+#include  "Ipf/IpfCpuCore.i"

+

+//----------------------------------------------------------------------------------

+// This module supports terminating CAR (Cache As RAM) stage. It copies all the

+// CAR data into real RAM and then makes a stack switch.

+

+// EFI_STATUS

+// SwitchCoreStacks (

+//   IN VOID  *EntryPoint,

+//   IN UINTN CopySize,

+//   IN VOID  *OldBase,

+//   IN VOID  *NewBase

+//   IN UINTN NewSP, OPTIONAL

+//   IN UINTN NewBSP OPTIONAL

+//   )

+// EFI_STATUS

+// SwitchCoreStacks (

+//   IN VOID  *EntryPointForContinuationFunction,

+//   IN UINTN StartupDescriptor,

+//   IN VOID  PEICorePointer,

+//   IN UINTN NewSP

+//   )

+//----------------------------------------------------------------------------------

+PROCEDURE_ENTRY (SwitchCoreStacks)

+

+        NESTED_SETUP (4,2,0,0)

+

+        // first save all stack registers in GPRs.

+        mov     r13 = in0;;             // this is a pointer to the PLABEL of the continuation function.

+        ld8     r16 = [r13],8;;         // r16 = address of continuation function from the PLABEL

+        ld8     gp = [r13];;            // gp  = gp of continuation function from the PLABEL

+        mov     b1 = r16;;

+

+        // save the parameters in r5, r6. these 2 seemed to be preserved across PAL calls

+        mov     r5 = in1;;              // this is the parameter1 to pass to the continuation function

+        mov     r6 = in2;;              // this is the parameter2 to pass to the continuation function

+        dep     r6=0,r6,63,1;;          // zero the bit 63.

+

+        mov     r8 = in3;;              // new stack pointer.

+

+        // r8 has the sp, this is 128K stack size, from this we will reserve 16K for the bspstore

+        movl    r15 = PEI_BSP_STORE_SIZE;;

+        sub     r8 = r8, r15;;

+        add     r15 = (GuardBand),r8;;  // some little buffer, now r15 will be our bspstore

+

+        // save the bspstore value to r4, save sp value to r7

+        mov     r4  = r15

+        mov     r7  = r8

+        mov     r16 = r8;;              // will be the new sp in uncache mode

+

+

+        alloc   r11=0,0,0,0;;           // Set 0-size frame

+        flushrs;;

+

+        mov     r21 = RSC_KERNEL_DISABLED;; // for rse disable

+        mov     ar.rsc = r21;;          // turn off RSE

+

+        add     sp = r0, r16            // transfer to the EFI stack

+        mov     ar.bspstore = r15       // switch to EFI BSP

+        invala                          // change of ar.bspstore needs invala.

+

+        mov     r19 = RSC_KERNEL_LAZ;;  // RSC enabled, Lazy mode

+        mov     ar.rsc = r19;;          // turn rse on, in kernel mode

+

+//-----------------------------------------------------------------------------------

+// Save here the meaningful stuff for next few lines and then make the PAL call.

+// Make PAL call to terminate the CAR status.

+        // AVL: do this only for recovery check call...

+

+        mov     r28=ar.k3;;

+        dep     r2 = r28,r0,0,8;;       // Extract Function bits from GR20.

+        cmp.eq  p6,p7 = RecoveryFn,r2;; // Is it Recovery check

+        (p7)  br.sptk.few DoneCARTermination; // if not, don't terminate car..

+

+TerminateCAR::

+

+        mov     r28 = ip;;

+        add     r28 = (DoneCARTerminationPALCall - TerminateCAR),r28;;

+        mov     b0 = r28

+

+        mov     r8 = ar.k5;;

+        mov     b6 = r8

+        mov     r28 = 0x208

+

+        mov     r29 = r0

+        mov     r30 = r0

+        mov     r31 = r0

+        mov     r8 = r0;;

+        br.sptk.few b6;;                // Call PAL-A call.

+

+DoneCARTerminationPALCall::

+

+// don't check error in soft sdv, it is always returning -1 for this call for some reason

+#if SOFT_SDV

+#else

+ReturnToPEIMain::

+        cmp.eq  p6,p7 = r8,r0;;

+        //

+        // dead loop if the PAL call failed, we have the CAR on but the stack is now pointing to memory

+        //

+        (p7) br.sptk.few ReturnToPEIMain;;

+        //

+        // PAL call successed,now the stack are in memory so come into cache mode

+        // instead of uncache mode

+        //

+

+        alloc   r11=0,0,0,0;;           // Set 0-size frame

+        flushrs;;

+

+        mov     r21 = RSC_KERNEL_DISABLED;; // for rse disable

+        mov     ar.rsc = r21;;          // turn off RSE

+

+        dep     r6 = 0,r6,63,1          // zero the bit 63

+        dep     r7 = 0,r7,63,1          // zero the bit 63

+        dep     r4 = 0,r4,63,1;;        // zero the bit 63

+        add     sp = r0, r7             // transfer to the EFI stack in cache mode

+        mov     ar.bspstore = r4        // switch to EFI BSP

+        invala                          // change of ar.bspstore needs invala.

+

+        mov     r19 = RSC_KERNEL_LAZ;;  // RSC enabled, Lazy mode

+        mov     ar.rsc = r19;;          // turn rse on, in kernel mode

+

+#endif

+

+DoneCARTermination::

+

+        // allocate a stack frame:

+        alloc   r11=0,2,2,0 ;;          // alloc  outs going to ensuing DXE IPL service

+                                                                                                // on the new stack

+        mov     out0 = r5;;

+        mov     out1 = r6;;

+

+        mov     r16 = b1;;

+        mov     b6 = r16;;

+        br.call.sptk.few b0=b6;;        // Call the continuation function

+

+        NESTED_RETURN

+

+PROCEDURE_EXIT(SwitchCoreStacks)

+//-----------------------------------------------------------------------------------

+

+//---------------------------------------------------------------------------------

+//++

+// GetHandOffStatus

+//

+// This routine is called by all processors simultaneously, to get some hand-off

+// status that has been captured by IPF dispatcher and recorded in kernel registers.

+//

+// Arguments :

+//

+// On Entry :  None.

+//

+// Return Value: Lid, R20Status.

+//

+//--

+//----------------------------------------------------------------------------------

+PROCEDURE_ENTRY (GetHandOffStatus)

+

+        NESTED_SETUP (0,2+0,0,0)

+

+        mov     r8 = ar.k6              // Health Status (Self test params)

+        mov     r9 = ar.k4              // LID bits

+        mov     r10 = ar.k3;;           // SAL_E entry state

+        mov     r11 = ar.k7             // Return address to PAL

+

+        NESTED_RETURN

+PROCEDURE_EXIT (GetHandOffStatus)

+//----------------------------------------------------------------------------------

+

+

diff --git a/MdeModulePkg/Core/Pei/Ipf/IpfPeiMain.h b/MdeModulePkg/Core/Pei/Ipf/IpfPeiMain.h
new file mode 100644
index 0000000..e5b160f
--- /dev/null
+++ b/MdeModulePkg/Core/Pei/Ipf/IpfPeiMain.h
@@ -0,0 +1,57 @@
+/*++

+

+Copyright (c) 2006, Intel Corporation

+All rights reserved. This program and the accompanying materials

+are licensed and made available under the terms and conditions of the BSD License

+which accompanies this distribution.  The full text of the license may be found at

+http://opensource.org/licenses/bsd-license.php

+

+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+Module Name:

+

+  IpfPeiMain.h

+

+Abstract:

+

+  Definition of IPF specific function

+

+Revision History

+

+--*/

+

+#ifndef _IPF_PEI_MAIN_H_

+#define _IPF_PEI_MAIN_H_

+

+//

+// Include common header file for this module.

+//

+#include "CommonHeader.h"

+

+#include <PeiMain.h>

+

+SAL_RETURN_REGS

+GetHandOffStatus (

+  VOID

+  )

+/*++

+

+Routine Description:

+

+   This routine is called by all processors simultaneously, to get some hand-off

+   status that has been captured by IPF dispatcher and recorded in kernel registers.

+  

+Arguments :

+

+  On Entry :  None.

+

+Returns:

+

+   Lid, R20Status.

+

+--*/

+

+;

+

+#endif

diff --git a/MdeModulePkg/Core/Pei/Ipf/Stack.c b/MdeModulePkg/Core/Pei/Ipf/Stack.c
new file mode 100644
index 0000000..600a41d
--- /dev/null
+++ b/MdeModulePkg/Core/Pei/Ipf/Stack.c
@@ -0,0 +1,63 @@
+/** @file

+  PeiSwitchStacks() function for PEI dispatcher.

+

+  Copyright (c) 2006 - 2007, Intel Corporation<BR>

+  All rights reserved. This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+  Module Name:  String.c

+

+**/

+

+//

+// Include common header file for this module.

+//

+#include "CommonHeader.h"

+

+#include <PeiMain.h>

+

+/**

+  Transfers control to a function starting with a new stack.

+

+  Transfers control to the function specified by EntryPoint using the new stack

+  specified by NewStack and passing in the parameters specified by Context1 and

+  Context2. Context1 and Context2 are optional and may be NULL. The function

+  EntryPoint must never return.

+

+  If EntryPoint is NULL, then ASSERT().

+  If NewStack is NULL, then ASSERT().

+

+  @param  EntryPoint  A pointer to function to call with the new stack.

+  @param  Context1    A pointer to the context to pass into the EntryPoint

+                      function.

+  @param  Context2    A pointer to the context to pass into the EntryPoint

+                      function.

+  @param  NewStack    A pointer to the new stack to use for the EntryPoint

+                      function.

+  @param  NewBsp      A pointer to the new BSP for the EntryPoint on IPF. It's

+                      Reserved on other architectures.

+

+**/

+VOID

+EFIAPI

+PeiSwitchStacks (

+  IN      SWITCH_STACK_ENTRY_POINT  EntryPoint,

+  IN      VOID                      *Context1,  OPTIONAL

+  IN      VOID                      *Context2,  OPTIONAL

+  IN      VOID                      *NewStack,

+  IN      VOID                      *NewBsp

+  )

+{

+  SwitchStack (

+    EntryPoint,

+    Context1,

+    Context2,

+    NewStack,

+    NewBsp

+    );

+}

diff --git a/MdeModulePkg/Core/Pei/Ipf/SwitchToCacheMode.c b/MdeModulePkg/Core/Pei/Ipf/SwitchToCacheMode.c
new file mode 100644
index 0000000..f4e90e1
--- /dev/null
+++ b/MdeModulePkg/Core/Pei/Ipf/SwitchToCacheMode.c
@@ -0,0 +1,76 @@
+/*++

+

+Copyright (c) 2006, Intel Corporation                                                         

+All rights reserved. This program and the accompanying materials                          

+are licensed and made available under the terms and conditions of the BSD License         

+which accompanies this distribution.  The full text of the license may be found at        

+http://opensource.org/licenses/bsd-license.php                                            

+                                                                                          

+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+

+Module Name:

+

+  SwitchToCacheMode.c

+

+Abstract:

+

+  Ipf CAR specific function used to switch to cache mode for the later memory access

+

+Revision History

+

+--*/

+

+//

+// Include common header file for this module.

+//

+#include "CommonHeader.h"

+

+#include "IpfPeiMain.h"

+#include "IpfCpuCore.i"

+

+VOID

+SwitchToCacheMode (

+  IN PEI_CORE_INSTANCE           *CoreData

+  )

+/*++

+

+Routine Description:

+

+ Switch the PHIT pointers to cache mode after InstallPeiMemory in CAR.

+

+Arguments:

+

+  CoreData   - The PEI core Private Data

+

+Returns:

+

+--*/

+{

+  EFI_HOB_HANDOFF_INFO_TABLE    *Phit;

+

+  if (CoreData == NULL) {

+    //

+    // the first call with CoreData as NULL.

+    //

+    return;

+  }

+  

+  if ((GetHandOffStatus().r10 & 0xFF) == RecoveryFn) {

+    CoreData->StackBase = CoreData->StackBase &  CACHE_MODE_ADDRESS_MASK;

+    CoreData->HobList.Raw = (UINT8 *)((UINTN)CoreData->HobList.Raw & CACHE_MODE_ADDRESS_MASK);

+

+    //

+    // Change the PHIT pointer value to cache mode

+    //

+    Phit = CoreData->HobList.HandoffInformationTable;

+

+    Phit->EfiMemoryTop        = Phit->EfiMemoryTop & CACHE_MODE_ADDRESS_MASK;

+    Phit->EfiFreeMemoryTop    = Phit->EfiFreeMemoryTop & CACHE_MODE_ADDRESS_MASK;

+    Phit->EfiMemoryBottom     = Phit->EfiMemoryBottom  & CACHE_MODE_ADDRESS_MASK;

+    Phit->EfiFreeMemoryBottom = Phit->EfiFreeMemoryBottom & CACHE_MODE_ADDRESS_MASK;

+    Phit->EfiEndOfHobList     = Phit->EfiEndOfHobList & CACHE_MODE_ADDRESS_MASK;

+  }

+

+  return;

+}