diff options
| author | rsun3 <rsun3@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-01-19 06:42:21 +0000 |
|---|---|---|
| committer | rsun3 <rsun3@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-01-19 06:42:21 +0000 |
| commit | 1ccdbf2a3e61fe9494fcd39432107ba0eb74f584 (patch) | |
| tree | f8f2bcf407258369b67023955eb4374ff1a8f901 /MdeModulePkg/Bus | |
| parent | cd730ec08d8fc5afc557ae7f39c948998cd96bbb (diff) | |
| download | edk2-1ccdbf2a3e61fe9494fcd39432107ba0eb74f584.zip edk2-1ccdbf2a3e61fe9494fcd39432107ba0eb74f584.tar.gz edk2-1ccdbf2a3e61fe9494fcd39432107ba0eb74f584.tar.bz2 | |
Improve coding style in MdeModulePkg.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9793 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdeModulePkg/Bus')
25 files changed, 634 insertions, 639 deletions
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c index 47ab1e3..aded0b3 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c @@ -10,7 +10,7 @@ This way avoids the control transfer on a shared port between EHCI and companion host
controller when UHCI gets attached earlier than EHCI and a USB 2.0 device inserts.
-Copyright (c) 2006 - 2009, Intel Corporation
+Copyright (c) 2006 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -1363,7 +1363,7 @@ EhcDriverBindingSupported ( // Test whether the controller belongs to Ehci type
//
if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) || (UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB)
- || ((UsbClassCReg.PI != PCI_IF_EHCI) && (UsbClassCReg.PI !=PCI_IF_UHCI))) {
+ || ((UsbClassCReg.ProgInterface != PCI_IF_EHCI) && (UsbClassCReg.ProgInterface !=PCI_IF_UHCI))) {
Status = EFI_UNSUPPORTED;
}
@@ -1598,7 +1598,7 @@ EhcDriverBindingStart ( // companion usb ehci host controller and force EHCI driver get attached to it before
// UHCI driver attaches to UHCI host controller.
//
- if ((UsbClassCReg.PI == PCI_IF_UHCI) &&
+ if ((UsbClassCReg.ProgInterface == PCI_IF_UHCI) &&
(UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&
(UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {
Status = PciIo->GetLocation (
@@ -1647,7 +1647,7 @@ EhcDriverBindingStart ( goto CLOSE_PCIIO;
}
- if ((UsbClassCReg.PI == PCI_IF_EHCI) &&
+ if ((UsbClassCReg.ProgInterface == PCI_IF_EHCI) &&
(UsbClassCReg.BaseCode == PCI_CLASS_SERIAL) &&
(UsbClassCReg.SubClassCode == PCI_CLASS_SERIAL_USB)) {
Status = Instance->GetLocation (
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h index 006632f..07abcaf 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h @@ -2,7 +2,7 @@ Provides some data struct used by EHCI controller driver.
-Copyright (c) 2006 - 2009, Intel Corporation
+Copyright (c) 2006 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -44,30 +44,31 @@ typedef struct _USB2_HC_DEV USB2_HC_DEV; #include "EhciDebug.h"
#include "ComponentName.h"
-typedef enum {
- EHC_1_MICROSECOND = 1,
- EHC_1_MILLISECOND = 1000 * EHC_1_MICROSECOND,
- EHC_1_SECOND = 1000 * EHC_1_MILLISECOND,
+//
+// EHC timeout experience values
+//
- //
- // EHCI register operation timeout, set by experience
- //
- EHC_RESET_TIMEOUT = 1 * EHC_1_SECOND,
- EHC_GENERIC_TIMEOUT = 10 * EHC_1_MILLISECOND,
+#define EHC_1_MICROSECOND 1
+#define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)
+#define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)
- //
- // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
- //
- EHC_ROOT_PORT_RECOVERY_STALL = 20 * EHC_1_MILLISECOND,
+//
+// EHCI register operation timeout, set by experience
+//
+#define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)
+#define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)
- //
- // Sync and Async transfer polling interval, set by experience,
- // and the unit of Async is 100us, means 50ms as interval.
- //
- EHC_SYNC_POLL_INTERVAL = 1 * EHC_1_MILLISECOND,
- EHC_ASYNC_POLL_INTERVAL = 50 * 10000U
-} EHC_TIMEOUT_EXPERIENCE_VALUE;
+//
+// Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
+//
+#define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
+//
+// Sync and Async transfer polling interval, set by experience,
+// and the unit of Async is 100us, means 50ms as interval.
+//
+#define EHC_SYNC_POLL_INTERVAL (1 * EHC_1_MILLISECOND)
+#define EHC_ASYNC_POLL_INTERVAL (50 * 10000U)
//
// EHC raises TPL to TPL_NOTIFY to serialize all its operations
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c index 892021c..76026ec 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.c @@ -2,7 +2,7 @@ This file provides the information dump support for EHCI when in debug mode.
-Copyright (c) 2007 - 2009, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -105,7 +105,7 @@ EhcDumpQtd ( DEBUG ((EFI_D_INFO, "Error Count : %d\n", QtdHw->ErrCnt));
DEBUG ((EFI_D_INFO, "Current Page : %d\n", QtdHw->CurPage));
- DEBUG ((EFI_D_INFO, "IOC : %d\n", QtdHw->IOC));
+ DEBUG ((EFI_D_INFO, "IOC : %d\n", QtdHw->Ioc));
DEBUG ((EFI_D_INFO, "Total Bytes : %d\n", QtdHw->TotalBytes));
DEBUG ((EFI_D_INFO, "Data Toggle : %d\n", QtdHw->DataToggle));
@@ -181,7 +181,7 @@ EhcDumpQh ( DEBUG ((EFI_D_INFO, "Error Count : %d\n", QhHw->ErrCnt));
DEBUG ((EFI_D_INFO, "Current Page : %d\n", QhHw->CurPage));
- DEBUG ((EFI_D_INFO, "IOC : %d\n", QhHw->IOC));
+ DEBUG ((EFI_D_INFO, "IOC : %d\n", QhHw->Ioc));
DEBUG ((EFI_D_INFO, "Total Bytes : %d\n", QhHw->TotalBytes));
DEBUG ((EFI_D_INFO, "Data Toggle : %d\n", QhHw->DataToggle));
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h index a995dc4..e1b57fa 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h @@ -2,7 +2,7 @@ This file contains the definination for host controller register operation routines.
-Copyright (c) 2007 - 2009, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,75 +16,77 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #ifndef _EFI_EHCI_REG_H_
#define _EFI_EHCI_REG_H_
+//
+// EHCI register offset
+//
+
+
+//
+// Capability register offset
+//
+#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
+#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
+#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
+
+//
+// Capability register bit definition
+//
+#define HCSP_NPORTS 0x0F // Number of root hub port
+#define HCCP_64BIT 0x01 // 64-bit addressing capability
+
+//
+// Operational register offset
+//
+#define EHC_USBCMD_OFFSET 0x0 // USB command register offset
+#define EHC_USBSTS_OFFSET 0x04 // Statue register offset
+#define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset
+#define EHC_FRINDEX_OFFSET 0x0C // Frame index offset
+#define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset
+#define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset
+#define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset
+#define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
+#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
+
+#define EHC_FRAME_LEN 1024
-typedef enum {
- //
- // Capability register offset
- //
- EHC_CAPLENGTH_OFFSET = 0, // Capability register length offset
- EHC_HCSPARAMS_OFFSET = 0x04, // Structural Parameters 04-07h
- EHC_HCCPARAMS_OFFSET = 0x08, // Capability parameters offset
-
- //
- // Capability register bit definition
- //
- HCSP_NPORTS = 0x0F, // Number of root hub port
- HCCP_64BIT = 0x01, // 64-bit addressing capability
-
- //
- // Operational register offset
- //
- EHC_USBCMD_OFFSET = 0x0, // USB command register offset
- EHC_USBSTS_OFFSET = 0x04, // Statue register offset
- EHC_USBINTR_OFFSET = 0x08, // USB interrutp offset
- EHC_FRINDEX_OFFSET = 0x0C, // Frame index offset
- EHC_CTRLDSSEG_OFFSET = 0x10, // Control data structure segment offset
- EHC_FRAME_BASE_OFFSET = 0x14, // Frame list base address offset
- EHC_ASYNC_HEAD_OFFSET = 0x18, // Next asynchronous list address offset
- EHC_CONFIG_FLAG_OFFSET = 0x40, // Configure flag register offset
- EHC_PORT_STAT_OFFSET = 0x44, // Port status/control offset
-
- EHC_FRAME_LEN = 1024,
-
- //
- // Register bit definition
- //
- CONFIGFLAG_ROUTE_EHC = 0x01, // Route port to EHC
-
- USBCMD_RUN = 0x01, // Run/stop
- USBCMD_RESET = 0x02, // Start the host controller reset
- USBCMD_ENABLE_PERIOD = 0x10, // Enable periodic schedule
- USBCMD_ENABLE_ASYNC = 0x20, // Enable asynchronous schedule
- USBCMD_IAAD = 0x40, // Interrupt on async advance doorbell
-
- USBSTS_IAA = 0x20, // Interrupt on async advance
- USBSTS_PERIOD_ENABLED = 0x4000, // Periodic schedule status
- USBSTS_ASYNC_ENABLED = 0x8000, // Asynchronous schedule status
- USBSTS_HALT = 0x1000, // Host controller halted
- USBSTS_SYS_ERROR = 0x10, // Host system error
- USBSTS_INTACK_MASK = 0x003F, // Mask for the interrupt ACK, the WC
- // (write clean) bits in USBSTS register
-
- PORTSC_CONN = 0x01, // Current Connect Status
- PORTSC_CONN_CHANGE = 0x02, // Connect Status Change
- PORTSC_ENABLED = 0x04, // Port Enable / Disable
- PORTSC_ENABLE_CHANGE = 0x08, // Port Enable / Disable Change
- PORTSC_OVERCUR = 0x10, // Over current Active
- PORTSC_OVERCUR_CHANGE = 0x20, // Over current Change
- PORSTSC_RESUME = 0x40, // Force Port Resume
- PORTSC_SUSPEND = 0x80, // Port Suspend State
- PORTSC_RESET = 0x100, // Port Reset
- PORTSC_LINESTATE_K = 0x400, // Line Status K-state
- PORTSC_LINESTATE_J = 0x800, // Line Status J-state
- PORTSC_POWER = 0x1000, // Port Power
- PORTSC_OWNER = 0x2000, // Port Owner
- PORTSC_CHANGE_MASK = 0x2A, // Mask of the port change bits,
- // they are WC (write clean)
- //
- // PCI Configuration Registers
- //
- EHC_BAR_INDEX = 0 /* how many bytes away from USB_BASE to 0x10 */
-}EHCI_REGISTER_OFFSET;
+//
+// Register bit definition
+//
+#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
+
+#define USBCMD_RUN 0x01 // Run/stop
+#define USBCMD_RESET 0x02 // Start the host controller reset
+#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
+#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
+#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
+
+#define USBSTS_IAA 0x20 // Interrupt on async advance
+#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
+#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
+#define USBSTS_HALT 0x1000 // Host controller halted
+#define USBSTS_SYS_ERROR 0x10 // Host system error
+#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
+ // (write clean) bits in USBSTS register
+
+#define PORTSC_CONN 0x01 // Current Connect Status
+#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
+#define PORTSC_ENABLED 0x04 // Port Enable / Disable
+#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
+#define PORTSC_OVERCUR 0x10 // Over current Active
+#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
+#define PORSTSC_RESUME 0x40 // Force Port Resume
+#define PORTSC_SUSPEND 0x80 // Port Suspend State
+#define PORTSC_RESET 0x100 // Port Reset
+#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
+#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
+#define PORTSC_POWER 0x1000 // Port Power
+#define PORTSC_OWNER 0x2000 // Port Owner
+#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
+ // they are WC (write clean)
+//
+// PCI Configuration Registers
+//
+#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
@@ -107,7 +109,7 @@ typedef struct { //
#pragma pack(1)
typedef struct {
- UINT8 PI;
+ UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
} USB_CLASSC;
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c index 2d8dc02..c1d44f5 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c @@ -2,7 +2,7 @@ EHCI transfer scheduling routines.
-Copyright (c) 2007 - 2009, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -881,7 +881,7 @@ EhcUpdateAsyncRequest ( QhHw->Pid = 0;
QhHw->ErrCnt = 0;
QhHw->CurPage = 0;
- QhHw->IOC = 0;
+ QhHw->Ioc = 0;
QhHw->TotalBytes = 0;
for (Index = 0; Index < 5; Index++) {
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.c index ba98f09..593652f 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.c @@ -3,7 +3,7 @@ This file contains URB request, each request is warpped in a
URB (Usb Request Block).
-Copyright (c) 2007 - 2009, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -68,7 +68,7 @@ EhcCreateQtd ( QtdHw->Status = QTD_STAT_ACTIVE;
QtdHw->Pid = PktId;
QtdHw->ErrCnt = QTD_MAX_ERR;
- QtdHw->IOC = 0;
+ QtdHw->Ioc = 0;
QtdHw->TotalBytes = 0;
QtdHw->DataToggle = Toggle;
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.h b/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.h index 2e06375..087dc6e 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciUrb.h @@ -3,7 +3,7 @@ This file contains URB request, each request is warpped in a
URB (Usb Request Block).
-Copyright (c) 2007 - 2009, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -22,61 +22,59 @@ typedef struct _EHC_QTD EHC_QTD; typedef struct _EHC_QH EHC_QH;
typedef struct _URB URB;
-typedef enum {
- //
- // Transfer types, used in URB to identify the transfer type
- //
- EHC_CTRL_TRANSFER = 0x01,
- EHC_BULK_TRANSFER = 0x02,
- EHC_INT_TRANSFER_SYNC = 0x04,
- EHC_INT_TRANSFER_ASYNC = 0x08,
+//
+// Transfer types, used in URB to identify the transfer type
+//
+#define EHC_CTRL_TRANSFER 0x01
+#define EHC_BULK_TRANSFER 0x02
+#define EHC_INT_TRANSFER_SYNC 0x04
+#define EHC_INT_TRANSFER_ASYNC 0x08
- EHC_QTD_SIG = SIGNATURE_32 ('U', 'S', 'B', 'T'),
- EHC_QH_SIG = SIGNATURE_32 ('U', 'S', 'B', 'H'),
- EHC_URB_SIG = SIGNATURE_32 ('U', 'S', 'B', 'R'),
+#define EHC_QTD_SIG SIGNATURE_32 ('U', 'S', 'B', 'T')
+#define EHC_QH_SIG SIGNATURE_32 ('U', 'S', 'B', 'H')
+#define EHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
- //
- // Hardware related bit definitions
- //
- EHC_TYPE_ITD = 0x00,
- EHC_TYPE_QH = 0x02,
- EHC_TYPE_SITD = 0x04,
- EHC_TYPE_FSTN = 0x06,
-
- QH_NAK_RELOAD = 3,
- QH_HSHBW_MULTI = 1,
-
- QTD_MAX_ERR = 3,
- QTD_PID_OUTPUT = 0x00,
- QTD_PID_INPUT = 0x01,
- QTD_PID_SETUP = 0x02,
-
- QTD_STAT_DO_OUT = 0,
- QTD_STAT_DO_SS = 0,
- QTD_STAT_DO_PING = 0x01,
- QTD_STAT_DO_CS = 0x02,
- QTD_STAT_TRANS_ERR = 0x08,
- QTD_STAT_BABBLE_ERR = 0x10,
- QTD_STAT_BUFF_ERR = 0x20,
- QTD_STAT_HALTED = 0x40,
- QTD_STAT_ACTIVE = 0x80,
- QTD_STAT_ERR_MASK = QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR,
-
- QTD_MAX_BUFFER = 4,
- QTD_BUF_LEN = 4096,
- QTD_BUF_MASK = 0x0FFF,
-
- QH_MICROFRAME_0 = 0x01,
- QH_MICROFRAME_1 = 0x02,
- QH_MICROFRAME_2 = 0x04,
- QH_MICROFRAME_3 = 0x08,
- QH_MICROFRAME_4 = 0x10,
- QH_MICROFRAME_5 = 0x20,
- QH_MICROFRAME_6 = 0x40,
- QH_MICROFRAME_7 = 0x80,
-
- USB_ERR_SHORT_PACKET = 0x200
-}EHCI_URB_FLAG_VALUE;
+//
+// Hardware related bit definitions
+//
+#define EHC_TYPE_ITD 0x00
+#define EHC_TYPE_QH 0x02
+#define EHC_TYPE_SITD 0x04
+#define EHC_TYPE_FSTN 0x06
+
+#define QH_NAK_RELOAD 3
+#define QH_HSHBW_MULTI 1
+
+#define QTD_MAX_ERR 3
+#define QTD_PID_OUTPUT 0x00
+#define QTD_PID_INPUT 0x01
+#define QTD_PID_SETUP 0x02
+
+#define QTD_STAT_DO_OUT 0
+#define QTD_STAT_DO_SS 0
+#define QTD_STAT_DO_PING 0x01
+#define QTD_STAT_DO_CS 0x02
+#define QTD_STAT_TRANS_ERR 0x08
+#define QTD_STAT_BABBLE_ERR 0x10
+#define QTD_STAT_BUFF_ERR 0x20
+#define QTD_STAT_HALTED 0x40
+#define QTD_STAT_ACTIVE 0x80
+#define QTD_STAT_ERR_MASK (QTD_STAT_TRANS_ERR | QTD_STAT_BABBLE_ERR | QTD_STAT_BUFF_ERR)
+
+#define QTD_MAX_BUFFER 4
+#define QTD_BUF_LEN 4096
+#define QTD_BUF_MASK 0x0FFF
+
+#define QH_MICROFRAME_0 0x01
+#define QH_MICROFRAME_1 0x02
+#define QH_MICROFRAME_2 0x04
+#define QH_MICROFRAME_3 0x08
+#define QH_MICROFRAME_4 0x10
+#define QH_MICROFRAME_5 0x20
+#define QH_MICROFRAME_6 0x40
+#define QH_MICROFRAME_7 0x80
+
+#define USB_ERR_SHORT_PACKET 0x200
//
// Fill in the hardware link point: pass in a EHC_QH/QH_HW
@@ -102,7 +100,7 @@ typedef struct { UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
- UINT32 IOC : 1;
+ UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
@@ -142,7 +140,7 @@ typedef struct { UINT32 Pid : 2;
UINT32 ErrCnt : 2;
UINT32 CurPage : 3;
- UINT32 IOC : 1;
+ UINT32 Ioc : 1;
UINT32 TotalBytes : 15;
UINT32 DataToggle : 1;
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.h b/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.h index ce0a782..3394c9b 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/UsbHcMem.h @@ -2,7 +2,7 @@ This file contains the definination for host controller memory management routines.
-Copyright (c) 2007 - 2009, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -24,15 +24,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define USB_HC_HIGH_32BIT(Addr64) \
((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
-typedef struct _USBHC_MEM_BLOCK {
+typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
+struct _USBHC_MEM_BLOCK {
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
- struct _USBHC_MEM_BLOCK *Next;
-} USBHC_MEM_BLOCK;
+ USBHC_MEM_BLOCK *Next;
+};
//
// USBHC_MEM_POOL is used to manage the memory used by USB
@@ -46,12 +47,13 @@ typedef struct _USBHC_MEM_POOL { USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
-typedef enum {
- USBHC_MEM_UNIT = 64, // Memory allocation unit, must be 2^n, n>4
+//
+// Memory allocation unit, must be 2^n, n>4
+//
+#define USBHC_MEM_UNIT 64
- USBHC_MEM_UNIT_MASK = USBHC_MEM_UNIT - 1,
- USBHC_MEM_DEFAULT_PAGES = 16
-} USBHC_MEM_UNIT_DATA;
+#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
+#define USBHC_MEM_DEFAULT_PAGES 16
#define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index bf0e67e..7d08246 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -1,7 +1,7 @@ /** @file
PCI emumeration support functions implementation for PCI Bus module.
-Copyright (c) 2006 - 2009, Intel Corporation
+Copyright (c) 2006 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -2062,7 +2062,7 @@ CreatePciIoDevice ( if ((PciIoDevice->SrIovCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport)& EFI_PCI_IOV_POLICY_SRIOV) != 0)) {
UINT16 VFStride;
UINT16 FirstVFOffset;
- UINT32 PFRID;
+ UINT32 PFRid;
UINT32 LastVF;
//
@@ -2098,8 +2098,8 @@ CreatePciIoDevice ( //
// Calculate LastVF
//
- PFRID = EFI_PCI_RID(Bus, Device, Func);
- LastVF = PFRID + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;
+ PFRid = EFI_PCI_RID(Bus, Device, Func);
+ LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;
//
// Calculate ReservedBusNum for this PF
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c index 1ed7902..c2d560b 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c +++ b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c @@ -2,7 +2,7 @@ The UHCI driver model and HC protocol routines.
-Copyright (c) 2004 - 2009, Intel Corporation
+Copyright (c) 2004 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -1411,7 +1411,7 @@ UhciDriverBindingSupported ( //
if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) ||
(UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB) ||
- (UsbClassCReg.PI != PCI_IF_UHCI)
+ (UsbClassCReg.ProgInterface != PCI_IF_UHCI)
) {
Status = EFI_UNSUPPORTED;
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h index eb61554..c2377bf 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h +++ b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h @@ -2,7 +2,7 @@ The definition for UHCI driver model and HC protocol routines.
-Copyright (c) 2004 - 2009, Intel Corporation
+Copyright (c) 2004 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -45,38 +45,39 @@ typedef struct _USB_HC_DEV USB_HC_DEV; #include "UhciDebug.h"
#include "ComponentName.h"
-typedef enum {
- UHC_1_MICROSECOND = 1,
- UHC_1_MILLISECOND = 1000 * UHC_1_MICROSECOND,
- UHC_1_SECOND = 1000 * UHC_1_MILLISECOND,
+//
+// UHC timeout experience values
+//
- //
- // UHCI register operation timeout, set by experience
- //
- UHC_GENERIC_TIMEOUT = UHC_1_SECOND,
+#define UHC_1_MICROSECOND 1
+#define UHC_1_MILLISECOND (1000 * UHC_1_MICROSECOND)
+#define UHC_1_SECOND (1000 * UHC_1_MILLISECOND)
- //
- // Wait for force global resume(FGR) complete, refers to
- // specification[UHCI11-2.1.1]
- //
- UHC_FORCE_GLOBAL_RESUME_STALL = 20 * UHC_1_MILLISECOND,
+//
+// UHCI register operation timeout, set by experience
+//
+#define UHC_GENERIC_TIMEOUT UHC_1_SECOND
- //
- // Wait for roothub port reset and recovery, reset stall
- // is set by experience, and recovery stall refers to
- // specification[UHCI11-2.1.1]
- //
- UHC_ROOT_PORT_RESET_STALL = 50 * UHC_1_MILLISECOND,
- UHC_ROOT_PORT_RECOVERY_STALL = 10 * UHC_1_MILLISECOND,
+//
+// Wait for force global resume(FGR) complete, refers to
+// specification[UHCI11-2.1.1]
+//
+#define UHC_FORCE_GLOBAL_RESUME_STALL (20 * UHC_1_MILLISECOND)
- //
- // Sync and Async transfer polling interval, set by experience,
- // and the unit of Async is 100us.
- //
- UHC_SYNC_POLL_INTERVAL = 1 * UHC_1_MILLISECOND,
- UHC_ASYNC_POLL_INTERVAL = 50 * 10000UL
-}UHC_TIMEOUT_EXPERIENCE_VALUE;
+//
+// Wait for roothub port reset and recovery, reset stall
+// is set by experience, and recovery stall refers to
+// specification[UHCI11-2.1.1]
+//
+#define UHC_ROOT_PORT_RESET_STALL (50 * UHC_1_MILLISECOND)
+#define UHC_ROOT_PORT_RECOVERY_STALL (10 * UHC_1_MILLISECOND)
+//
+// Sync and Async transfer polling interval, set by experience,
+// and the unit of Async is 100us.
+//
+#define UHC_SYNC_POLL_INTERVAL (1 * UHC_1_MILLISECOND)
+#define UHC_ASYNC_POLL_INTERVAL (50 * 10000UL)
//
// UHC raises TPL to TPL_NOTIFY to serialize all its operations
@@ -88,7 +89,7 @@ typedef enum { #pragma pack(1)
typedef struct {
- UINT8 PI;
+ UINT8 ProgInterface;
UINT8 SubClassCode;
UINT8 BaseCode;
} USB_CLASSC;
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h b/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h index 8d7a076..d9bdc43 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h @@ -2,7 +2,7 @@ The definition for UHCI register operation routines.
-Copyright (c) 2007 - 2008, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,81 +16,83 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #ifndef _EFI_UHCI_REG_H_
#define _EFI_UHCI_REG_H_
-typedef enum {
- UHCI_FRAME_NUM = 1024,
-
- //
- // Register offset and PCI related staff
- //
- USB_BAR_INDEX = 4,
-
- USBCMD_OFFSET = 0,
- USBSTS_OFFSET = 2,
- USBINTR_OFFSET = 4,
- USBPORTSC_OFFSET = 0x10,
- USB_FRAME_NO_OFFSET = 6,
- USB_FRAME_BASE_OFFSET = 8,
- USB_EMULATION_OFFSET = 0xC0,
-
- //
- // Packet IDs
- //
- SETUP_PACKET_ID = 0x2D,
- INPUT_PACKET_ID = 0x69,
- OUTPUT_PACKET_ID = 0xE1,
- ERROR_PACKET_ID = 0x55,
-
- //
- // USB port status and control bit definition.
- //
- USBPORTSC_CCS = BIT0, // Current Connect Status
- USBPORTSC_CSC = BIT1, // Connect Status Change
- USBPORTSC_PED = BIT2, // Port Enable / Disable
- USBPORTSC_PEDC = BIT3, // Port Enable / Disable Change
- USBPORTSC_LSL = BIT4, // Line Status Low BIT
- USBPORTSC_LSH = BIT5, // Line Status High BIT
- USBPORTSC_RD = BIT6, // Resume Detect
- USBPORTSC_LSDA = BIT8, // Low Speed Device Attached
- USBPORTSC_PR = BIT9, // Port Reset
- USBPORTSC_SUSP = BIT12, // Suspend
-
- //
- // UHCI Spec said it must implement 2 ports each host at least,
- // and if more, check whether the bit7 of PORTSC is always 1.
- // So here assume the max of port number each host is 16.
- //
- USB_MAX_ROOTHUB_PORT = 0x0F,
-
- //
- // Command register bit definitions
- //
- USBCMD_RS = BIT0, // Run/Stop
- USBCMD_HCRESET = BIT1, // Host reset
- USBCMD_GRESET = BIT2, // Global reset
- USBCMD_EGSM = BIT3, // Global Suspend Mode
- USBCMD_FGR = BIT4, // Force Global Resume
- USBCMD_SWDBG = BIT5, // SW Debug mode
- USBCMD_CF = BIT6, // Config Flag (sw only)
- USBCMD_MAXP = BIT7, // Max Packet (0 = 32, 1 = 64)
-
- //
- // USB Status register bit definitions
- //
- USBSTS_USBINT = BIT0, // Interrupt due to IOC
- USBSTS_ERROR = BIT1, // Interrupt due to error
- USBSTS_RD = BIT2, // Resume Detect
- USBSTS_HSE = BIT3, // Host System Error
- USBSTS_HCPE = BIT4, // Host Controller Process Error
- USBSTS_HCH = BIT5, // HC Halted
-
- USBTD_ACTIVE = BIT7, // TD is still active
- USBTD_STALLED = BIT6, // TD is stalled
- USBTD_BUFFERR = BIT5, // Buffer underflow or overflow
- USBTD_BABBLE = BIT4, // Babble condition
- USBTD_NAK = BIT3, // NAK is received
- USBTD_CRC = BIT2, // CRC/Time out error
- USBTD_BITSTUFF = BIT1 // Bit stuff error
-}UHCI_REGISTER_OFFSET;
+//
+// UHCI register offset
+//
+
+#define UHCI_FRAME_NUM 1024
+
+//
+// Register offset and PCI related staff
+//
+#define USB_BAR_INDEX 4
+
+#define USBCMD_OFFSET 0
+#define USBSTS_OFFSET 2
+#define USBINTR_OFFSET 4
+#define USBPORTSC_OFFSET 0x10
+#define USB_FRAME_NO_OFFSET 6
+#define USB_FRAME_BASE_OFFSET 8
+#define USB_EMULATION_OFFSET 0xC0
+
+//
+// Packet IDs
+//
+#define SETUP_PACKET_ID 0x2D
+#define INPUT_PACKET_ID 0x69
+#define OUTPUT_PACKET_ID 0xE1
+#define ERROR_PACKET_ID 0x55
+
+//
+// USB port status and control bit definition.
+//
+#define USBPORTSC_CCS BIT0 // Current Connect Status
+#define USBPORTSC_CSC BIT1 // Connect Status Change
+#define USBPORTSC_PED BIT2 // Port Enable / Disable
+#define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change
+#define USBPORTSC_LSL BIT4 // Line Status Low BIT
+#define USBPORTSC_LSH BIT5 // Line Status High BIT
+#define USBPORTSC_RD BIT6 // Resume Detect
+#define USBPORTSC_LSDA BIT8 // Low Speed Device Attached
+#define USBPORTSC_PR BIT9 // Port Reset
+#define USBPORTSC_SUSP BIT12 // Suspend
+
+//
+// UHCI Spec said it must implement 2 ports each host at least,
+// and if more, check whether the bit7 of PORTSC is always 1.
+// So here assume the max of port number each host is 16.
+//
+#define USB_MAX_ROOTHUB_PORT 0x0F
+
+//
+// Command register bit definitions
+//
+#define USBCMD_RS BIT0 // Run/Stop
+#define USBCMD_HCRESET BIT1 // Host reset
+#define USBCMD_GRESET BIT2 // Global reset
+#define USBCMD_EGSM BIT3 // Global Suspend Mode
+#define USBCMD_FGR BIT4 // Force Global Resume
+#define USBCMD_SWDBG BIT5 // SW Debug mode
+#define USBCMD_CF BIT6 // Config Flag (sw only)
+#define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)
+
+//
+// USB Status register bit definitions
+//
+#define USBSTS_USBINT BIT0 // Interrupt due to IOC
+#define USBSTS_ERROR BIT1 // Interrupt due to error
+#define USBSTS_RD BIT2 // Resume Detect
+#define USBSTS_HSE BIT3 // Host System Error
+#define USBSTS_HCPE BIT4 // Host Controller Process Error
+#define USBSTS_HCH BIT5 // HC Halted
+
+#define USBTD_ACTIVE BIT7 // TD is still active
+#define USBTD_STALLED BIT6 // TD is stalled
+#define USBTD_BUFFERR BIT5 // Buffer underflow or overflow
+#define USBTD_BABBLE BIT4 // Babble condition
+#define USBTD_NAK BIT3 // NAK is received
+#define USBTD_CRC BIT2 // CRC/Time out error
+#define USBTD_BITSTUFF BIT1 // Bit stuff error
/**
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h index b4b7c4c..310dfa0 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h @@ -2,7 +2,7 @@ The definition for EHCI register operation routines.
-Copyright (c) 2007, 2009, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -17,21 +17,18 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define _EFI_UHCI_SCHED_H_
-typedef enum {
- UHCI_ASYNC_INT_SIGNATURE = SIGNATURE_32 ('u', 'h', 'c', 'a'),
-
- //
- // The failure mask for USB transfer return status. If any of
- // these bit is set, the transfer failed. EFI_USB_ERR_NOEXECUTE
- // and EFI_USB_ERR_NAK are not considered as error condition:
- // the transfer is still going on.
- //
- USB_ERR_FAIL_MASK = EFI_USB_ERR_STALL | EFI_USB_ERR_BUFFER |
- EFI_USB_ERR_BABBLE | EFI_USB_ERR_CRC |
- EFI_USB_ERR_TIMEOUT | EFI_USB_ERR_BITSTUFF |
- EFI_USB_ERR_SYSTEM
+#define UHCI_ASYNC_INT_SIGNATURE SIGNATURE_32 ('u', 'h', 'c', 'a')
+//
+// The failure mask for USB transfer return status. If any of
+// these bit is set, the transfer failed. EFI_USB_ERR_NOEXECUTE
+// and EFI_USB_ERR_NAK are not considered as error condition:
+// the transfer is still going on.
+//
+#define USB_ERR_FAIL_MASK (EFI_USB_ERR_STALL | EFI_USB_ERR_BUFFER | \
+ EFI_USB_ERR_BABBLE | EFI_USB_ERR_CRC | \
+ EFI_USB_ERR_TIMEOUT | EFI_USB_ERR_BITSTUFF | \
+ EFI_USB_ERR_SYSTEM)
-}UHCI_ERR_FAIL_MASK;
//
// Structure to return the result of UHCI QH execution.
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h b/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h index 6b71442..5ad9f97 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UsbHcMem.h @@ -2,7 +2,7 @@ This file contains the definination for host controller memory management routines
-Copyright (c) 2007, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -25,15 +25,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
-typedef struct _USBHC_MEM_BLOCK {
+typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;
+struct _USBHC_MEM_BLOCK {
UINT8 *Bits; // Bit array to record which unit is allocated
UINTN BitsLen;
UINT8 *Buf;
UINT8 *BufHost;
UINTN BufLen; // Memory size in bytes
VOID *Mapping;
- struct _USBHC_MEM_BLOCK *Next;
-} USBHC_MEM_BLOCK;
+ USBHC_MEM_BLOCK *Next;
+};
//
// USBHC_MEM_POOL is used to manage the memory used by USB
@@ -47,12 +48,13 @@ typedef struct _USBHC_MEM_POOL { USBHC_MEM_BLOCK *Head;
} USBHC_MEM_POOL;
-typedef enum {
- USBHC_MEM_UNIT = 64, // Memory allocation unit, must be 2^n, n>4
+//
+// Memory allocation unit, must be 2^n, n>4
+//
+#define USBHC_MEM_UNIT 64
- USBHC_MEM_UNIT_MASK = USBHC_MEM_UNIT - 1,
- USBHC_MEM_DEFAULT_PAGES = 16
-}UHCI_MEM_UNIT_DATA;
+#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)
+#define USBHC_MEM_DEFAULT_PAGES 16
#define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))
diff --git a/MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBus.h b/MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBus.h index 1c0c376..fb63d0a 100644 --- a/MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBus.h +++ b/MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBus.h @@ -1,7 +1,7 @@ /** @file
Header file for SCSI Bus Driver.
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -38,11 +38,13 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define SCSI_IO_DEV_SIGNATURE SIGNATURE_32 ('s', 'c', 'i', 'o')
+typedef union {
+ UINT32 Scsi;
+ UINT8 ExtScsi[4];
+} SCSI_ID;
+
typedef struct _SCSI_TARGET_ID {
- union {
- UINT32 Scsi;
- UINT8 ExtScsi[4];
- } ScsiId;
+ SCSI_ID ScsiId;
UINT8 ExtScsiId[12];
}SCSI_TARGET_ID;
diff --git a/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.h b/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.h index 638be99..9bc5cf6 100644 --- a/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.h +++ b/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.h @@ -2,7 +2,7 @@ Usb Bus Driver Binding and Bus IO Protocol.
-Copyright (c) 2004 - 2007, Intel Corporation
+Copyright (c) 2004 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -47,81 +47,83 @@ typedef struct _USB_HUB_API USB_HUB_API; #include "UsbHub.h"
#include "UsbEnumer.h"
-typedef enum {
- USB_MAX_LANG_ID = 16,
- USB_MAX_INTERFACE = 16,
- USB_MAX_DEVICES = 128,
+//
+// USB bus timeout experience values
+//
- USB_BUS_1_MILLISECOND = 1000,
+#define USB_MAX_LANG_ID 16
+#define USB_MAX_INTERFACE 16
+#define USB_MAX_DEVICES 128
- //
- // Roothub and hub's polling interval, set by experience,
- // The unit of roothub is 100us, means 1s as interval, and
- // the unit of hub is 1ms, means 64ms as interval.
- //
- USB_ROOTHUB_POLL_INTERVAL = 1000 * 10000U,
- USB_HUB_POLL_INTERVAL = 64,
+#define USB_BUS_1_MILLISECOND 1000
- //
- // Wait for port stable to work, refers to specification
- // [USB20-9.1.2]
- //
- USB_WAIT_PORT_STABLE_STALL = 100 * USB_BUS_1_MILLISECOND,
+//
+// Roothub and hub's polling interval, set by experience,
+// The unit of roothub is 100us, means 1s as interval, and
+// the unit of hub is 1ms, means 64ms as interval.
+//
+#define USB_ROOTHUB_POLL_INTERVAL (1000 * 10000U)
+#define USB_HUB_POLL_INTERVAL 64
- //
- // Wait for port statue reg change, set by experience
- //
- USB_WAIT_PORT_STS_CHANGE_STALL = 5 * USB_BUS_1_MILLISECOND,
+//
+// Wait for port stable to work, refers to specification
+// [USB20-9.1.2]
+//
+#define USB_WAIT_PORT_STABLE_STALL (100 * USB_BUS_1_MILLISECOND)
- //
- // Wait for set device address, refers to specification
- // [USB20-9.2.6.3, it says 2ms]
- //
- USB_SET_DEVICE_ADDRESS_STALL = 20 * USB_BUS_1_MILLISECOND,
+//
+// Wait for port statue reg change, set by experience
+//
+#define USB_WAIT_PORT_STS_CHANGE_STALL (5 * USB_BUS_1_MILLISECOND)
- //
- // Wait for retry max packet size, set by experience
- //
- USB_RETRY_MAX_PACK_SIZE_STALL = 100 * USB_BUS_1_MILLISECOND,
+//
+// Wait for set device address, refers to specification
+// [USB20-9.2.6.3, it says 2ms]
+//
+#define USB_SET_DEVICE_ADDRESS_STALL (20 * USB_BUS_1_MILLISECOND)
- //
- // Wait for hub port power-on, refers to specification
- // [USB20-11.23.2]
- //
- USB_SET_PORT_POWER_STALL = 2 * USB_BUS_1_MILLISECOND,
+//
+// Wait for retry max packet size, set by experience
+//
+#define USB_RETRY_MAX_PACK_SIZE_STALL (100 * USB_BUS_1_MILLISECOND)
- //
- // Wait for port reset, refers to specification
- // [USB20-7.1.7.5, it says 10ms for hub and 50ms for
- // root hub]
- //
- USB_SET_PORT_RESET_STALL = 20 * USB_BUS_1_MILLISECOND,
- USB_SET_ROOT_PORT_RESET_STALL = 50 * USB_BUS_1_MILLISECOND,
+//
+// Wait for hub port power-on, refers to specification
+// [USB20-11.23.2]
+//
+#define USB_SET_PORT_POWER_STALL (2 * USB_BUS_1_MILLISECOND)
- //
- // Wait for clear roothub port reset, set by experience
- //
- USB_CLR_ROOT_PORT_RESET_STALL = 20 * USB_BUS_1_MILLISECOND,
+//
+// Wait for port reset, refers to specification
+// [USB20-7.1.7.5, it says 10ms for hub and 50ms for
+// root hub]
+//
+#define USB_SET_PORT_RESET_STALL (20 * USB_BUS_1_MILLISECOND)
+#define USB_SET_ROOT_PORT_RESET_STALL (50 * USB_BUS_1_MILLISECOND)
- //
- // Wait for set roothub port enable, set by experience
- //
- USB_SET_ROOT_PORT_ENABLE_STALL = 20 * USB_BUS_1_MILLISECOND,
+//
+// Wait for clear roothub port reset, set by experience
+//
+#define USB_CLR_ROOT_PORT_RESET_STALL (20 * USB_BUS_1_MILLISECOND)
- //
- // Send general device request timeout.
- //
- // The USB Specification 2.0, section 11.24.1 recommends a value of
- // 50 milliseconds. We use a value of 100 milliseconds to work
- // around slower hubs and devices.
- //
- USB_GENERAL_DEVICE_REQUEST_TIMEOUT = 100,
+//
+// Wait for set roothub port enable, set by experience
+//
+#define USB_SET_ROOT_PORT_ENABLE_STALL (20 * USB_BUS_1_MILLISECOND)
- //
- // Send clear feature request timeout, set by experience
- //
- USB_CLEAR_FEATURE_REQUEST_TIMEOUT = 10
-}USB_BUS_TIMEOUT_EXPERIENCE_VALUE;
+//
+// Send general device request timeout.
+//
+// The USB Specification 2.0, section 11.24.1 recommends a value of
+// 50 milliseconds. We use a value of 100 milliseconds to work
+// around slower hubs and devices.
+//
+#define USB_GENERAL_DEVICE_REQUEST_TIMEOUT 100
+
+//
+// Send clear feature request timeout, set by experience
+//
+#define USB_CLEAR_FEATURE_REQUEST_TIMEOUT 10
//
// Bus raises TPL to TPL_NOTIFY to serialize all its operations
diff --git a/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbDesc.h b/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbDesc.h index dd7868b..ae189f7 100644 --- a/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbDesc.h +++ b/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbDesc.h @@ -2,7 +2,7 @@ Manage Usb Descriptor List
-Copyright (c) 2007, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,9 +16,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #ifndef _USB_DESCRIPTOR_H_
#define _USB_DESCRIPTOR_H_
-typedef enum {
- USB_MAX_INTERFACE_SETTING = 8
-}USB_INTERFACE_SETTING_MAX;
+#define USB_MAX_INTERFACE_SETTING 8
//
// The RequestType in EFI_USB_DEVICE_REQUEST is composed of
diff --git a/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbHub.h b/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbHub.h index af4897a..f63eb50 100644 --- a/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbHub.h +++ b/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbHub.h @@ -2,7 +2,7 @@ The definition for USB hub.
-Copyright (c) 2007, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -21,72 +21,65 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define USB_ENDPOINT_ADDR(EpAddr) ((EpAddr) & 0x7F)
#define USB_ENDPOINT_TYPE(Desc) ((Desc)->Attributes & USB_ENDPOINT_TYPE_MASK)
-typedef enum {
- USB_DESC_TYPE_HUB = 0x29,
-
- //
- // Hub class control transfer target
- //
- USB_HUB_TARGET_HUB = 0,
- USB_HUB_TARGET_PORT = 3,
-
- //
- // HUB class specific contrl transfer request type
- //
- USB_HUB_REQ_GET_STATUS = 0,
- USB_HUB_REQ_CLEAR_FEATURE = 1,
- USB_HUB_REQ_SET_FEATURE = 3,
- USB_HUB_REQ_GET_DESC = 6,
- USB_HUB_REQ_SET_DESC = 7,
- USB_HUB_REQ_CLEAR_TT = 8,
- USB_HUB_REQ_RESET_TT = 9,
- USB_HUB_REQ_GET_TT_STATE = 10,
- USB_HUB_REQ_STOP_TT = 11,
-
-
- //
- // USB hub class feature selector
- //
- USB_HUB_C_HUB_LOCAL_POWER = 0,
- USB_HUB_C_HUB_OVER_CURRENT = 1,
- USB_HUB_PORT_CONNECTION = 0,
- USB_HUB_PORT_ENABLE = 1,
- USB_HUB_PORT_SUSPEND = 2,
- USB_HUB_PORT_OVER_CURRENT = 3,
- USB_HUB_PORT_RESET = 4,
- USB_HUB_PORT_POWER = 8,
- USB_HUB_PORT_LOW_SPEED = 9,
- USB_HUB_C_PORT_CONNECT = 16,
- USB_HUB_C_PORT_ENABLE = 17,
- USB_HUB_C_PORT_SUSPEND = 18,
- USB_HUB_C_PORT_OVER_CURRENT = 19,
- USB_HUB_C_PORT_RESET = 20,
- USB_HUB_PORT_TEST = 21,
- USB_HUB_PORT_INDICATOR = 22,
-
- //
- // USB hub power control method. In gang power control
- //
- USB_HUB_GANG_POWER_CTRL = 0,
- USB_HUB_PORT_POWER_CTRL = 0x01,
-
- //
- // USB hub status bits
- //
- USB_HUB_STAT_LOCAL_POWER = 0x01,
- USB_HUB_STAT_OVER_CURRENT = 0x02,
- USB_HUB_STAT_C_LOCAL_POWER = 0x01,
- USB_HUB_STAT_C_OVER_CURRENT = 0x02,
-
- USB_HUB_CLASS_CODE = 0x09,
- USB_HUB_SUBCLASS_CODE = 0x00,
-
- //
- // Host software return timeout if port status doesn't change
- // after 500ms(LOOP * STALL = 100 * 5ms), set by experience
- //
- USB_WAIT_PORT_STS_CHANGE_LOOP = 100
-}USB_HUB_FLAGS_VALUE;
+
+#define USB_DESC_TYPE_HUB 0x29
+//
+// Hub class control transfer target
+//
+#define USB_HUB_TARGET_HUB 0
+#define USB_HUB_TARGET_PORT 3
+//
+// HUB class specific contrl transfer request type
+//
+#define USB_HUB_REQ_GET_STATUS 0
+#define USB_HUB_REQ_CLEAR_FEATURE 1
+#define USB_HUB_REQ_SET_FEATURE 3
+#define USB_HUB_REQ_GET_DESC 6
+#define USB_HUB_REQ_SET_DESC 7
+#define USB_HUB_REQ_CLEAR_TT 8
+#define USB_HUB_REQ_RESET_TT 9
+#define USB_HUB_REQ_GET_TT_STATE 10
+#define USB_HUB_REQ_STOP_TT 11
+//
+// USB hub class feature selector
+//
+#define USB_HUB_C_HUB_LOCAL_POWER 0
+#define USB_HUB_C_HUB_OVER_CURRENT 1
+#define USB_HUB_PORT_CONNECTION 0
+#define USB_HUB_PORT_ENABLE 1
+#define USB_HUB_PORT_SUSPEND 2
+#define USB_HUB_PORT_OVER_CURRENT 3
+#define USB_HUB_PORT_RESET 4
+#define USB_HUB_PORT_POWER 8
+#define USB_HUB_PORT_LOW_SPEED 9
+#define USB_HUB_C_PORT_CONNECT 16
+#define USB_HUB_C_PORT_ENABLE 17
+#define USB_HUB_C_PORT_SUSPEND 18
+#define USB_HUB_C_PORT_OVER_CURRENT 19
+#define USB_HUB_C_PORT_RESET 20
+#define USB_HUB_PORT_TEST 21
+#define USB_HUB_PORT_INDICATOR 22
+//
+// USB hub power control method. In gang power control
+//
+#define USB_HUB_GANG_POWER_CTRL 0
+#define USB_HUB_PORT_POWER_CTRL 0x01
+//
+// USB hub status bits
+//
+#define USB_HUB_STAT_LOCAL_POWER 0x01
+#define USB_HUB_STAT_OVER_CURRENT 0x02
+#define USB_HUB_STAT_C_LOCAL_POWER 0x01
+#define USB_HUB_STAT_C_OVER_CURRENT 0x02
+
+#define USB_HUB_CLASS_CODE 0x09
+#define USB_HUB_SUBCLASS_CODE 0x00
+
+//
+// Host software return timeout if port status doesn't change
+// after 500ms(LOOP * STALL = 100 * 5ms), set by experience
+//
+#define USB_WAIT_PORT_STS_CHANGE_LOOP 100
#pragma pack(1)
//
diff --git a/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMass.h b/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMass.h index 33b2381..b89014a 100644 --- a/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMass.h +++ b/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMass.h @@ -2,7 +2,7 @@ Definition of USB Mass Storage Class and its value, USB Mass Transport Protocol,
and other common definitions.
-Copyright (c) 2007 - 2008, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -38,36 +38,34 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define USB_IS_INTERRUPT_ENDPOINT(Attribute) (((Attribute) & (BIT0 | BIT1)) == USB_ENDPOINT_INTERRUPT)
#define USB_IS_ERROR(Result, Error) (((Result) & (Error)) != 0)
-typedef enum {
- //
- // Usb mass storage class code
- //
- USB_MASS_STORE_CLASS = 0x08,
-
- //
- // Usb mass storage subclass code, specify the command set used.
- //
- USB_MASS_STORE_RBC = 0x01, ///< Reduced Block Commands
- USB_MASS_STORE_8020I = 0x02, ///< SFF-8020i, typically a CD/DVD device
- USB_MASS_STORE_QIC = 0x03, ///< Typically a tape device
- USB_MASS_STORE_UFI = 0x04, ///< Typically a floppy disk driver device
- USB_MASS_STORE_8070I = 0x05, ///< SFF-8070i, typically a floppy disk driver device.
- USB_MASS_STORE_SCSI = 0x06, ///< SCSI transparent command set
-
- //
- // Usb mass storage protocol code, specify the transport protocol
- //
- USB_MASS_STORE_CBI0 = 0x00, ///< CBI protocol with command completion interrupt
- USB_MASS_STORE_CBI1 = 0x01, ///< CBI protocol without command completion interrupt
- USB_MASS_STORE_BOT = 0x50, ///< Bulk-Only Transport
-
- USB_MASS_1_MILLISECOND = 1000,
- USB_MASS_1_SECOND = 1000 * USB_MASS_1_MILLISECOND,
-
- USB_MASS_CMD_SUCCESS = 0,
- USB_MASS_CMD_FAIL,
- USB_MASS_CMD_PERSISTENT
-} USB_MASS_DEV_CLASS_AND_VALUE;
+//
+// Usb mass storage class code
+//
+#define USB_MASS_STORE_CLASS 0x08
+
+//
+// Usb mass storage subclass code, specify the command set used.
+//
+#define USB_MASS_STORE_RBC 0x01 ///< Reduced Block Commands
+#define USB_MASS_STORE_8020I 0x02 ///< SFF-8020i, typically a CD/DVD device
+#define USB_MASS_STORE_QIC 0x03 ///< Typically a tape device
+#define USB_MASS_STORE_UFI 0x04 ///< Typically a floppy disk driver device
+#define USB_MASS_STORE_8070I 0x05 ///< SFF-8070i, typically a floppy disk driver device.
+#define USB_MASS_STORE_SCSI 0x06 ///< SCSI transparent command set
+
+//
+// Usb mass storage protocol code, specify the transport protocol
+//
+#define USB_MASS_STORE_CBI0 0x00 ///< CBI protocol with command completion interrupt
+#define USB_MASS_STORE_CBI1 0x01 ///< CBI protocol without command completion interrupt
+#define USB_MASS_STORE_BOT 0x50 ///< Bulk-Only Transport
+
+#define USB_MASS_1_MILLISECOND 1000
+#define USB_MASS_1_SECOND (1000 * USB_MASS_1_MILLISECOND)
+
+#define USB_MASS_CMD_SUCCESS 0
+#define USB_MASS_CMD_FAIL 1
+#define USB_MASS_CMD_PERSISTENT 2
/**
Initializes USB transport protocol.
diff --git a/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBoot.c b/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBoot.c index cc6f2e8..1b200bb 100644 --- a/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBoot.c +++ b/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBoot.c @@ -2,7 +2,7 @@ Implementation of the command set of USB Mass Storage Specification
for Bootability, Revision 1.0.
-Copyright (c) 2007 - 2008, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -92,10 +92,10 @@ UsbBootRequestSense ( case USB_BOOT_SENSE_NOT_READY:
Status = EFI_DEVICE_ERROR;
- if (SenseData.ASC == USB_BOOT_ASC_NO_MEDIA) {
+ if (SenseData.Asc == USB_BOOT_ASC_NO_MEDIA) {
Media->MediaPresent = FALSE;
Status = EFI_NO_MEDIA;
- } else if (SenseData.ASC == USB_BOOT_ASC_NOT_READY) {
+ } else if (SenseData.Asc == USB_BOOT_ASC_NOT_READY) {
Status = EFI_NOT_READY;
}
break;
@@ -106,7 +106,7 @@ UsbBootRequestSense ( case USB_BOOT_SENSE_UNIT_ATTENTION:
Status = EFI_DEVICE_ERROR;
- if (SenseData.ASC == USB_BOOT_ASC_MEDIA_CHANGE) {
+ if (SenseData.Asc == USB_BOOT_ASC_MEDIA_CHANGE) {
//
// If MediaChange, reset ReadOnly and new MediaId
//
@@ -129,8 +129,8 @@ UsbBootRequestSense ( DEBUG ((EFI_D_INFO, "UsbBootRequestSense: (%r) with sense key %x/%x/%x\n",
Status,
USB_BOOT_SENSE_KEY (SenseData.SenseKey),
- SenseData.ASC,
- SenseData.ASCQ
+ SenseData.Asc,
+ SenseData.Ascq
));
return Status;
diff --git a/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBoot.h b/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBoot.h index cd66d82..91a21fc 100644 --- a/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBoot.h +++ b/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBoot.h @@ -2,7 +2,7 @@ Definition of the command set of USB Mass Storage Specification
for Bootability, Revision 1.0.
-Copyright (c) 2007 - 2008, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -18,79 +18,77 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #include "UsbMass.h"
-typedef enum {
- //
- // The opcodes of various USB boot commands:
- // INQUIRY/REQUEST_SENSE are "No Timeout Commands" as specified
- // by Multi-Media Commands (MMC) set.
- // Others are "Group 1 Timeout Commands". That is,
- // they should be retried if driver is ready.
- //
- USB_BOOT_INQUIRY_OPCODE = 0x12,
- USB_BOOT_REQUEST_SENSE_OPCODE = 0x03,
- USB_BOOT_MODE_SENSE10_OPCODE = 0x5A,
- USB_BOOT_READ_CAPACITY_OPCODE = 0x25,
- USB_BOOT_TEST_UNIT_READY_OPCODE = 0x00,
- USB_BOOT_READ10_OPCODE = 0x28,
- USB_BOOT_WRITE10_OPCODE = 0x2A,
-
- USB_SCSI_MODE_SENSE6_OPCODE = 0x1A,
-
- //
- // The Sense Key part of the sense data. Sense data has three levels:
- // Sense key, Additional Sense Code and Additional Sense Code Qualifier
- //
- USB_BOOT_SENSE_NO_SENSE = 0x00, ///< No sense key
- USB_BOOT_SENSE_RECOVERED = 0x01, ///< Last command succeed with recovery actions
- USB_BOOT_SENSE_NOT_READY = 0x02, ///< Device not ready
- USB_BOOT_SNESE_MEDIUM_ERROR = 0X03, ///< Failed probably because flaw in the media
- USB_BOOT_SENSE_HARDWARE_ERROR = 0X04, ///< Non-recoverable hardware failure
- USB_BOOT_SENSE_ILLEGAL_REQUEST = 0X05, ///< Illegal parameters in the request
- USB_BOOT_SENSE_UNIT_ATTENTION = 0X06, ///< Removable medium may have been changed
- USB_BOOT_SENSE_DATA_PROTECT = 0X07, ///< Write protected
- USB_BOOT_SENSE_BLANK_CHECK = 0X08, ///< Blank/non-blank medium while reading/writing
- USB_BOOT_SENSE_VENDOR = 0X09, ///< Vendor specific sense key
- USB_BOOT_SENSE_ABORTED = 0X0B, ///< Command aborted by the device
- USB_BOOT_SENSE_VOLUME_OVERFLOW = 0x0D, ///< Partition overflow
- USB_BOOT_SENSE_MISCOMPARE = 0x0E, ///< Source data mis-match while verfying.
-
- USB_BOOT_ASC_NOT_READY = 0x04,
- USB_BOOT_ASC_NO_MEDIA = 0x3A,
- USB_BOOT_ASC_MEDIA_CHANGE = 0x28,
-
- //
- // Supported PDT codes, or Peripheral Device Type
- //
- USB_PDT_DIRECT_ACCESS = 0x00, ///< Direct access device
- USB_PDT_CDROM = 0x05, ///< CDROM
- USB_PDT_OPTICAL = 0x07, ///< Non-CD optical disks
- USB_PDT_SIMPLE_DIRECT = 0x0E, ///< Simplified direct access device
-
- //
- // Other parameters, Max carried size is 512B * 128 = 64KB
- //
- USB_BOOT_IO_BLOCKS = 128,
-
- //
- // Retry mass command times, set by experience
- //
- USB_BOOT_COMMAND_RETRY = 5,
- USB_BOOT_INIT_MEDIA_RETRY = 5,
-
- //
- // Wait for unit ready command, set by experience
- //
- USB_BOOT_RETRY_UNIT_READY_STALL = 500 * USB_MASS_1_MILLISECOND,
-
- //
- // Mass command timeout, refers to specification[USB20-9.2.6.1]
- //
- // USB2.0 Spec define the up-limit timeout 5s for all command. USB floppy,
- // USB CD-Rom and iPod devices are much slower than USB key when reponse
- // most of commands, So we set 5s as timeout here.
- //
- USB_BOOT_GENERAL_CMD_TIMEOUT = 5 * USB_MASS_1_SECOND
-}USB_BOOT_OPTCODE;
+//
+// The opcodes of various USB boot commands:
+// INQUIRY/REQUEST_SENSE are "No Timeout Commands" as specified
+// by Multi-Media Commands (MMC) set.
+// Others are "Group 1 Timeout Commands". That is,
+// they should be retried if driver is ready.
+//
+#define USB_BOOT_INQUIRY_OPCODE 0x12
+#define USB_BOOT_REQUEST_SENSE_OPCODE 0x03
+#define USB_BOOT_MODE_SENSE10_OPCODE 0x5A
+#define USB_BOOT_READ_CAPACITY_OPCODE 0x25
+#define USB_BOOT_TEST_UNIT_READY_OPCODE 0x00
+#define USB_BOOT_READ10_OPCODE 0x28
+#define USB_BOOT_WRITE10_OPCODE 0x2A
+
+#define USB_SCSI_MODE_SENSE6_OPCODE 0x1A
+
+//
+// The Sense Key part of the sense data. Sense data has three levels:
+// Sense key, Additional Sense Code and Additional Sense Code Qualifier
+//
+#define USB_BOOT_SENSE_NO_SENSE 0x00 ///< No sense key
+#define USB_BOOT_SENSE_RECOVERED 0x01 ///< Last command succeed with recovery actions
+#define USB_BOOT_SENSE_NOT_READY 0x02 ///< Device not ready
+#define USB_BOOT_SNESE_MEDIUM_ERROR 0X03 ///< Failed probably because flaw in the media
+#define USB_BOOT_SENSE_HARDWARE_ERROR 0X04 ///< Non-recoverable hardware failure
+#define USB_BOOT_SENSE_ILLEGAL_REQUEST 0X05 ///< Illegal parameters in the request
+#define USB_BOOT_SENSE_UNIT_ATTENTION 0X06 ///< Removable medium may have been changed
+#define USB_BOOT_SENSE_DATA_PROTECT 0X07 ///< Write protected
+#define USB_BOOT_SENSE_BLANK_CHECK 0X08 ///< Blank/non-blank medium while reading/writing
+#define USB_BOOT_SENSE_VENDOR 0X09 ///< Vendor specific sense key
+#define USB_BOOT_SENSE_ABORTED 0X0B ///< Command aborted by the device
+#define USB_BOOT_SENSE_VOLUME_OVERFLOW 0x0D ///< Partition overflow
+#define USB_BOOT_SENSE_MISCOMPARE 0x0E ///< Source data mis-match while verfying.
+
+#define USB_BOOT_ASC_NOT_READY 0x04
+#define USB_BOOT_ASC_NO_MEDIA 0x3A
+#define USB_BOOT_ASC_MEDIA_CHANGE 0x28
+
+//
+// Supported PDT codes, or Peripheral Device Type
+//
+#define USB_PDT_DIRECT_ACCESS 0x00 ///< Direct access device
+#define USB_PDT_CDROM 0x05 ///< CDROM
+#define USB_PDT_OPTICAL 0x07 ///< Non-CD optical disks
+#define USB_PDT_SIMPLE_DIRECT 0x0E ///< Simplified direct access device
+
+//
+// Other parameters, Max carried size is 512B * 128 = 64KB
+//
+#define USB_BOOT_IO_BLOCKS 128
+
+//
+// Retry mass command times, set by experience
+//
+#define USB_BOOT_COMMAND_RETRY 5
+#define USB_BOOT_INIT_MEDIA_RETRY 5
+
+//
+// Wait for unit ready command, set by experience
+//
+#define USB_BOOT_RETRY_UNIT_READY_STALL (500 * USB_MASS_1_MILLISECOND)
+
+//
+// Mass command timeout, refers to specification[USB20-9.2.6.1]
+//
+// USB2.0 Spec define the up-limit timeout 5s for all command. USB floppy,
+// USB CD-Rom and iPod devices are much slower than USB key when reponse
+// most of commands, So we set 5s as timeout here.
+//
+#define USB_BOOT_GENERAL_CMD_TIMEOUT (5 * USB_MASS_1_SECOND)
//
// The required commands are INQUIRY, READ CAPACITY, TEST UNIT READY,
@@ -193,8 +191,8 @@ typedef struct { UINT8 Infor[4];
UINT8 AddLen; ///< Additional Sense length, 10
UINT8 Reserved1[4];
- UINT8 ASC; ///< Additional Sense Code
- UINT8 ASCQ; ///< Additional Sense Code Qualifier
+ UINT8 Asc; ///< Additional Sense Code
+ UINT8 Ascq; ///< Additional Sense Code Qualifier
UINT8 Reserverd2[4];
} USB_BOOT_REQUEST_SENSE_DATA;
diff --git a/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h b/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h index 63d9fec..341adce 100644 --- a/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h +++ b/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h @@ -3,7 +3,7 @@ based on the "Universal Serial Bus Mass Storage Class Bulk-Only
Transport" Revision 1.0, September 31, 1999.
-Copyright (c) 2007 - 2008, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -21,41 +21,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. extern USB_MASS_TRANSPORT mUsbBotTransport;
-typedef enum {
- //
- // Usb Bulk-Only class specfic request
- //
- USB_BOT_RESET_REQUEST = 0xFF, ///< Bulk-Only Mass Storage Reset
- USB_BOT_GETLUN_REQUEST = 0xFE, ///< Get Max Lun
- USB_BOT_CBW_SIGNATURE = 0x43425355, ///< dCBWSignature, tag the packet as CBW
- USB_BOT_CSW_SIGNATURE = 0x53425355, ///< dCSWSignature, tag the packet as CSW
- USB_BOT_MAX_LUN = 0x0F, ///< Lun number is from 0 to 15
- USB_BOT_MAX_CMDLEN = 16, ///< Maxium number of command from command set
-
- //
- // Usb BOT command block status values
- //
- USB_BOT_COMMAND_OK = 0x00, ///< Command passed, good status
- USB_BOT_COMMAND_FAILED = 0x01, ///< Command failed
- USB_BOT_COMMAND_ERROR = 0x02, ///< Phase error, need to reset the device
-
- //
- // Usb Bot retry to get CSW, refers to specification[BOT10-5.3, it says 2 times]
- //
- USB_BOT_RECV_CSW_RETRY = 3,
-
- //
- // Usb Bot wait device reset complete, set by experience
- //
- USB_BOT_RESET_DEVICE_STALL = 100 * USB_MASS_1_MILLISECOND,
-
- //
- // Usb Bot transport timeout, set by experience
- //
- USB_BOT_SEND_CBW_TIMEOUT = 3 * USB_MASS_1_SECOND,
- USB_BOT_RECV_CSW_TIMEOUT = 3 * USB_MASS_1_SECOND,
- USB_BOT_RESET_DEVICE_TIMEOUT = 3 * USB_MASS_1_SECOND
-} USB_BOT_SUBCLASS;
+//
+// Usb Bulk-Only class specfic request
+//
+#define USB_BOT_RESET_REQUEST 0xFF ///< Bulk-Only Mass Storage Reset
+#define USB_BOT_GETLUN_REQUEST 0xFE ///< Get Max Lun
+#define USB_BOT_CBW_SIGNATURE 0x43425355 ///< dCBWSignature, tag the packet as CBW
+#define USB_BOT_CSW_SIGNATURE 0x53425355 ///< dCSWSignature, tag the packet as CSW
+#define USB_BOT_MAX_LUN 0x0F ///< Lun number is from 0 to 15
+#define USB_BOT_MAX_CMDLEN 16 ///< Maxium number of command from command set
+
+//
+// Usb BOT command block status values
+//
+#define USB_BOT_COMMAND_OK 0x00 ///< Command passed, good status
+#define USB_BOT_COMMAND_FAILED 0x01 ///< Command failed
+#define USB_BOT_COMMAND_ERROR 0x02 ///< Phase error, need to reset the device
+
+//
+// Usb Bot retry to get CSW, refers to specification[BOT10-5.3, it says 2 times]
+//
+#define USB_BOT_RECV_CSW_RETRY 3
+
+//
+// Usb Bot wait device reset complete, set by experience
+//
+#define USB_BOT_RESET_DEVICE_STALL (100 * USB_MASS_1_MILLISECOND)
+
+//
+// Usb Bot transport timeout, set by experience
+//
+#define USB_BOT_SEND_CBW_TIMEOUT (3 * USB_MASS_1_SECOND)
+#define USB_BOT_RECV_CSW_TIMEOUT (3 * USB_MASS_1_SECOND)
+#define USB_BOT_RESET_DEVICE_TIMEOUT (3 * USB_MASS_1_SECOND)
#pragma pack(1)
///
diff --git a/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassCbi.h b/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassCbi.h index 05f3795..aeffb5f 100644 --- a/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassCbi.h +++ b/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassCbi.h @@ -2,7 +2,7 @@ Defination for the USB mass storage Control/Bulk/Interrupt (CBI) transport,
according to USB Mass Storage Class Control/Bulk/Interrupt (CBI) Transport, Revision 1.1.
-Copyright (c) 2007 - 2008, Intel Corporation
+Copyright (c) 2007 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -21,25 +21,20 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. extern USB_MASS_TRANSPORT mUsbCbi0Transport;
extern USB_MASS_TRANSPORT mUsbCbi1Transport;
-typedef enum {
- USB_CBI_MAX_PACKET_NUM = 16,
- USB_CBI_RESET_CMD_LEN = 12,
-
- //
- // USB CBI retry C/B/I transport times, set by experience
- //
- USB_CBI_MAX_RETRY = 3,
-
- //
- // Time to wait for USB CBI reset to complete, set by experience
- //
- USB_CBI_RESET_DEVICE_STALL = 50 * USB_MASS_1_MILLISECOND,
-
- //
- // USB CBI transport timeout, set by experience
- //
- USB_CBI_RESET_DEVICE_TIMEOUT = 1 * USB_MASS_1_SECOND
-} USB_CBI_DATA;
+#define USB_CBI_MAX_PACKET_NUM 16
+#define USB_CBI_RESET_CMD_LEN 12
+//
+// USB CBI retry C/B/I transport times, set by experience
+//
+#define USB_CBI_MAX_RETRY 3
+//
+// Time to wait for USB CBI reset to complete, set by experience
+//
+#define USB_CBI_RESET_DEVICE_STALL (50 * USB_MASS_1_MILLISECOND)
+//
+// USB CBI transport timeout, set by experience
+//
+#define USB_CBI_RESET_DEVICE_TIMEOUT (1 * USB_MASS_1_SECOND)
typedef struct {
//
diff --git a/MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointer.h b/MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointer.h index 1159ffc..2fa0864 100644 --- a/MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointer.h +++ b/MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointer.h @@ -1,7 +1,7 @@ /** @file
Helper routine and corresponding data struct used by USB Mouse Absolute Pointer Driver.
-Copyright (c) 2004 - 2008, Intel Corporation
+Copyright (c) 2004 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -79,20 +79,23 @@ typedef struct { ///
/// General HID Item structure
///
+
+typedef union {
+ UINT8 U8;
+ UINT16 U16;
+ UINT32 U32;
+ INT8 I8;
+ INT16 I16;
+ INT32 I32;
+ UINT8 *LongData;
+} HID_DATA;
+
typedef struct {
- UINT16 Format;
- UINT8 Size;
- UINT8 Type;
- UINT8 Tag;
- union {
- UINT8 U8;
- UINT16 U16;
- UINT32 U32;
- INT8 I8;
- INT16 I16;
- INT32 I32;
- UINT8 *LongData;
- } Data;
+ UINT16 Format;
+ UINT8 Size;
+ UINT8 Type;
+ UINT8 Tag;
+ HID_DATA Data;
} HID_ITEM;
#define USB_MOUSE_ABSOLUTE_POINTER_DEV_FROM_MOUSE_PROTOCOL(a) \
diff --git a/MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouse.h b/MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouse.h index e2f43fc..36d337e 100644 --- a/MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouse.h +++ b/MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouse.h @@ -1,7 +1,7 @@ /** @file
Helper routine and corresponding data struct used by USB Mouse Driver.
-Copyright (c) 2004 - 2008, Intel Corporation
+Copyright (c) 2004 - 2010, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -79,20 +79,23 @@ typedef struct { ///
/// General HID Item structure
///
+
+typedef union {
+ UINT8 U8;
+ UINT16 U16;
+ UINT32 U32;
+ INT8 I8;
+ INT16 I16;
+ INT32 I32;
+ UINT8 *LongData;
+} HID_DATA;
+
typedef struct {
- UINT16 Format;
- UINT8 Size;
- UINT8 Type;
- UINT8 Tag;
- union {
- UINT8 U8;
- UINT16 U16;
- UINT32 U32;
- INT8 I8;
- INT16 I16;
- INT32 I32;
- UINT8 *LongData;
- } Data;
+ UINT16 Format;
+ UINT8 Size;
+ UINT8 Type;
+ UINT8 Tag;
+ HID_DATA Data;
} HID_ITEM;
#define USB_MOUSE_DEV_FROM_MOUSE_PROTOCOL(a) \
|