diff options
| author | vanjeff <vanjeff@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-07-24 09:54:50 +0000 |
|---|---|---|
| committer | vanjeff <vanjeff@6f19259b-4bc3-4df7-8a09-765794883524> | 2007-07-24 09:54:50 +0000 |
| commit | 50fa1b3a86faee57ca597e778c9db4ed4233f83e (patch) | |
| tree | 9f7576b32fc70dc3f7bac646fc84c84861648e13 /MdeModulePkg/Bus/Pci | |
| parent | d19862fe4f9d0e5c5886c94a1e115f231d8fd302 (diff) | |
| download | edk2-50fa1b3a86faee57ca597e778c9db4ed4233f83e.zip edk2-50fa1b3a86faee57ca597e778c9db4ed4233f83e.tar.gz edk2-50fa1b3a86faee57ca597e778c9db4ed4233f83e.tar.bz2 | |
Sync USB modules with main trunk.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@3423 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdeModulePkg/Bus/Pci')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.h | 4 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c | 71 |
2 files changed, 75 insertions, 0 deletions
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.h b/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.h index 247021b..4df8e9e 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciDebug.h @@ -150,10 +150,14 @@ EhcDumpBuf ( #define EHC_DEBUG(arg) EhcDebug arg
#define EHC_ERROR(arg) EhcError arg
#define EHC_DUMP_QH(arg) EhcDumpQh arg
+ #define EHC_DUMP_QTD(arg) EhcDumpQtd arg
+ #define EHC_DUMP_BUF(arg) EhcDumpBuf arg
#else
#define EHC_DEBUG(arg)
#define EHC_ERROR(arg)
#define EHC_DUMP_QH(arg)
+ #define EHC_DUMP_QTD(arg)
+ #define EHC_DUMP_BUF(arg)
#endif
#endif
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c index b13e407..4c2dc86 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c @@ -771,6 +771,67 @@ EhciDelAllAsyncIntTransfers ( }
}
+STATIC
+EFI_STATUS
+EhcFlushAsyncIntMap (
+ IN USB2_HC_DEV *Ehc,
+ IN URB *Urb
+ )
+/*++
+
+Routine Description:
+
+ Flush data from PCI controller specific address to mapped system
+ memory address.
+
+Arguments:
+
+ Ehc - The EHCI device
+ Urb - The URB to unmap
+
+Returns:
+
+ EFI_SUCCESS - Success to flush data to mapped system memory
+ EFI_DEVICE_ERROR - Fail to flush data to mapped system memory
+
+--*/
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINTN Len;
+ VOID *Map;
+
+ PciIo = Ehc->PciIo;
+ Len = Urb->DataLen;
+
+ if (Urb->Ep.Direction == EfiUsbDataIn) {
+ MapOp = EfiPciIoOperationBusMasterWrite;
+ } else {
+ MapOp = EfiPciIoOperationBusMasterRead;
+ }
+
+ Status = PciIo->Unmap (PciIo, Urb->DataMap);
+ if (EFI_ERROR (Status)) {
+ goto ON_ERROR;
+ }
+
+ Urb->DataMap = NULL;
+
+ Status = PciIo->Map (PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
+ if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
+ goto ON_ERROR;
+ }
+
+ Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
+ Urb->DataMap = Map;
+ return EFI_SUCCESS;
+
+ON_ERROR:
+ return EFI_DEVICE_ERROR;
+}
+
/**
@@ -873,6 +934,7 @@ EhcMoniteAsyncRequests ( BOOLEAN Finished;
UINT8 *ProcBuf;
URB *Urb;
+ EFI_STATUS Status;
OldTpl = gBS->RaiseTPL (EHC_TPL);
Ehc = (USB2_HC_DEV *) Context;
@@ -891,6 +953,15 @@ EhcMoniteAsyncRequests ( }
//
+ // Flush any PCI posted write transactions from a PCI host
+ // bridge to system memory.
+ //
+ Status = EhcFlushAsyncIntMap (Ehc, Urb);
+ if (EFI_ERROR (Status)) {
+ EHC_ERROR (("EhcMoniteAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
+ }
+
+ //
// Allocate a buffer then copy the transferred data for user.
// If failed to allocate the buffer, update the URB for next
// round of transfer. Ignore the data of this round.
|